Ask Slashdot: What's the Best All-Purpose RISC-V System on a Chip Family?
(Monday March 16, 2026 @06:00PM (EditorDavid)
from the RISC-y-business dept.)
Slashdot reader [1]SysEngineer does embedded/IoT work, but "I want to pick a single system-on-a-chip architecture family and commit to it across multiple product lines — sensor nodes up through edge gateways... I've been on one platform for years and want to know what embedded engineers are actually running in production before I commit!"
And "the family needs to scale — cheap and small at the low end, capable of running Linux on the bigger variants!"
Their requirements?
WiFi + BLE required
LoRaWAN a nice-to-have.
Low power modes that actually work in the field, not just on the datasheet.
Full peripheral set — SPI, I2C, UART, ADC, timers, CAN.
A toolchain and runtime support, support multi threads...
Slashdot reader [2]Gravis Zero is [3]skeptical all the requirements can be met. "If you want embedded, you get embedded. If you want to run a big OS, you get one that will run a big OS."
But Slashdot reader [4]SysEngineer believes "The obvious architecture candidates are ARM, STM, and RISC-V" — and specifically they want to hear your experiences with the RISC-V choices. "What would you standardize on today if you were starting fresh? And how does real-world toolchain and community support hold up compared to the marketing?"
Share your own thoughts and experiences in the comments.
What's the best all-purpose RISC-V system on a chip family?
[1] https://www.slashdot.org/~SysEngineer
[2] https://www.slashdot.org/~Gravis+Zero
[3] https://slashdot.org/comments.pl?cid=66042984&sid=23940912&tid=384
[4] https://www.slashdot.org/~SysEngineer
And "the family needs to scale — cheap and small at the low end, capable of running Linux on the bigger variants!"
Their requirements?
WiFi + BLE required
LoRaWAN a nice-to-have.
Low power modes that actually work in the field, not just on the datasheet.
Full peripheral set — SPI, I2C, UART, ADC, timers, CAN.
A toolchain and runtime support, support multi threads...
Slashdot reader [2]Gravis Zero is [3]skeptical all the requirements can be met. "If you want embedded, you get embedded. If you want to run a big OS, you get one that will run a big OS."
But Slashdot reader [4]SysEngineer believes "The obvious architecture candidates are ARM, STM, and RISC-V" — and specifically they want to hear your experiences with the RISC-V choices. "What would you standardize on today if you were starting fresh? And how does real-world toolchain and community support hold up compared to the marketing?"
Share your own thoughts and experiences in the comments.
What's the best all-purpose RISC-V system on a chip family?
[1] https://www.slashdot.org/~SysEngineer
[2] https://www.slashdot.org/~Gravis+Zero
[3] https://slashdot.org/comments.pl?cid=66042984&sid=23940912&tid=384
[4] https://www.slashdot.org/~SysEngineer