Chinese RISC-V project teases 2025 debut of freely licensed advanced chip design
(2025/01/08)
- Reference: 1736321293
- News link: https://www.theregister.co.uk/2025/01/08/chinese_riscv_project_teases_2025/
- Source link:
A key figure in in China’s drive to develop processors based on the RISC-V instruction set architecture has said the project will deliver in 2025, perhaps with a design that could be a datacenter contender.
The prospect of a 2025 debut appeared on Sunday in a [1]post to Chinese social media service Weibo, penned by Yungang Bao of the Institute of Computing Technology at the Chinese Academy of Sciences.
The academy has created a project called Xiangshan that aims to use the permissively licensed RISC-V ISA to create a high-performance chip, with the Scala source code to the designs [2]openly available .
[3]
Bao is a leader of the project, and has [4]described the team's ambition to create a company that does for RISC-V what Red Hat did for Linux – although he said that before Red Hat [5]changed the way it made the source code of RHEL available to the public.
[6]
[7]
The Xiangshan project has previously aspired to six-monthly releases, though it appears its latest design to be taped out was a second-gen chip named Nanhu that emerged in late 2023. That silicon ran at 2GHz and was built on a 14nm process node.
The project has since worked on a third-gen design, named Kunminghu, and published the image below depicting an overview of its non-trivial micro-architecture.
[8]
An overview of the Kunminghu RISC-V micro-architecture ... click to enlarge ( [9]Source )
Just what it will be possible to build with a 64-bit RISC-V Kunminghu isn’t known, though the project’s most recent [10]progress report mentions simulated testing of a processor that runs at 3GHz.
Bao’s post acknowledges that the project hasn’t progressed as quickly as hoped and argues that’s because developing high-end chips is hard.
[11]
The Xiangshan project therefore spent all of 2024 “continuously optimizing the area and power consumption of the third-generation Xiangshan (Kunming Lake architecture), and finally achieved a gap of less than 8 percent compared with N2.”
That’s almost certainly a reference to Arm’s Neoverse 2 CPU core, which the Softbank-owned chip design champ recommends for use in the cloud, HPC, and machine learning applications. We’re pretty sure that Neoverse 2 is the tech [12]Microsoft used for the Cobalt 100 CPU it uses to power Arm servers it rents in the Azure cloud.
[13]RISC-V is making moves, but it has work to do if it wants to hit the mainstream
[14]RISC-V's AI champion just scored $693M cash infusion
[15]TSMC reportedly cuts off RISC-V chip designer linked to Huawei accelerators
[16]RISC-V reaches milestone with RVA23 profile ratification
If Xiangshan can deliver a design with similar power it will be enormously significant, for three reasons.
One is that RISC-V is mostly used for modest silicon. Leveling it up, or providing another processor that levels it up, would be a big step forward.
Another is that the project uses the [17]Mulan PSL-2.0 license, which grants a “perpetual, worldwide, royalty-free, non-exclusive, irrevocable copyright license to reproduce, use, modify, or distribute” IP, with modification or not. Xiangshan designs would therefore be free, a contrast to Arm’s license-based business model and the closed proprietary products from Intel and AMD. One only needs to consider how Linux came to dominate the operating system market to understand the potential for Xiangshan to shake up the industry and make trouble for established chipmakers.
[18]
A third reason is that the Xiangshan project was started to help China become less dependent on foreign entities. If it delivers processors to rival from those from established players, sanctions that prevent the sale of advanced silicon to the Middle Kingdom may become less potent.
Of course, it may be years before that happens. Despite Bao’s promises, Xiangshan’s third-gen designs are yet to debut or be baked into silicon, from what we can tell; the project has already blown plenty of deadlines; moving from design to working silicon can take ages … and so can the work to encourage developers to target a platform.
Bao’s post is therefore exciting, but the Xiangshan story will play out for many years. ®
Get our [19]Tech Resources
[1] https://m.weibo.cn/status/5119262297426864
[2] https://github.com/OpenXiangShan/XiangShan?tab=readme-ov-file
[3] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[4] https://www.theregister.com/2021/12/06/china_riscv/
[5] https://www.theregister.com/2023/06/23/red_hat_centos_move/
[6] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[7] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[8] https://regmedia.co.uk/2025/01/08/handout_kunminghu.jpg
[9] https://github.com/OpenXiangShan/XiangShan/blob/master/images/xs-arch-kunminghu.svg
[10] https://github.com/OpenXiangShan/XiangShan-doc/commit/e2d9cd6f0e779ff788630d34f1ef7ff106bb8f74
[11] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[12] https://www.theregister.com/2024/10/21/microsoft_arm_cobalt_100_cpu/
[13] https://www.theregister.com/2025/01/02/riscv_journey_to_mainstream/
[14] https://www.theregister.com/2024/12/04/riscv_ai_champion_investment/
[15] https://www.theregister.com/2024/10/28/tsmc_sophgo_huawei/
[16] https://www.theregister.com/2024/10/23/rva23_profile_ratified/
[17] https://spdx.org/licenses/MulanPSL-2.0.html
[18] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[19] https://whitepapers.theregister.com/
The prospect of a 2025 debut appeared on Sunday in a [1]post to Chinese social media service Weibo, penned by Yungang Bao of the Institute of Computing Technology at the Chinese Academy of Sciences.
The academy has created a project called Xiangshan that aims to use the permissively licensed RISC-V ISA to create a high-performance chip, with the Scala source code to the designs [2]openly available .
[3]
Bao is a leader of the project, and has [4]described the team's ambition to create a company that does for RISC-V what Red Hat did for Linux – although he said that before Red Hat [5]changed the way it made the source code of RHEL available to the public.
[6]
[7]
The Xiangshan project has previously aspired to six-monthly releases, though it appears its latest design to be taped out was a second-gen chip named Nanhu that emerged in late 2023. That silicon ran at 2GHz and was built on a 14nm process node.
The project has since worked on a third-gen design, named Kunminghu, and published the image below depicting an overview of its non-trivial micro-architecture.
[8]
An overview of the Kunminghu RISC-V micro-architecture ... click to enlarge ( [9]Source )
Just what it will be possible to build with a 64-bit RISC-V Kunminghu isn’t known, though the project’s most recent [10]progress report mentions simulated testing of a processor that runs at 3GHz.
Bao’s post acknowledges that the project hasn’t progressed as quickly as hoped and argues that’s because developing high-end chips is hard.
[11]
The Xiangshan project therefore spent all of 2024 “continuously optimizing the area and power consumption of the third-generation Xiangshan (Kunming Lake architecture), and finally achieved a gap of less than 8 percent compared with N2.”
That’s almost certainly a reference to Arm’s Neoverse 2 CPU core, which the Softbank-owned chip design champ recommends for use in the cloud, HPC, and machine learning applications. We’re pretty sure that Neoverse 2 is the tech [12]Microsoft used for the Cobalt 100 CPU it uses to power Arm servers it rents in the Azure cloud.
[13]RISC-V is making moves, but it has work to do if it wants to hit the mainstream
[14]RISC-V's AI champion just scored $693M cash infusion
[15]TSMC reportedly cuts off RISC-V chip designer linked to Huawei accelerators
[16]RISC-V reaches milestone with RVA23 profile ratification
If Xiangshan can deliver a design with similar power it will be enormously significant, for three reasons.
One is that RISC-V is mostly used for modest silicon. Leveling it up, or providing another processor that levels it up, would be a big step forward.
Another is that the project uses the [17]Mulan PSL-2.0 license, which grants a “perpetual, worldwide, royalty-free, non-exclusive, irrevocable copyright license to reproduce, use, modify, or distribute” IP, with modification or not. Xiangshan designs would therefore be free, a contrast to Arm’s license-based business model and the closed proprietary products from Intel and AMD. One only needs to consider how Linux came to dominate the operating system market to understand the potential for Xiangshan to shake up the industry and make trouble for established chipmakers.
[18]
A third reason is that the Xiangshan project was started to help China become less dependent on foreign entities. If it delivers processors to rival from those from established players, sanctions that prevent the sale of advanced silicon to the Middle Kingdom may become less potent.
Of course, it may be years before that happens. Despite Bao’s promises, Xiangshan’s third-gen designs are yet to debut or be baked into silicon, from what we can tell; the project has already blown plenty of deadlines; moving from design to working silicon can take ages … and so can the work to encourage developers to target a platform.
Bao’s post is therefore exciting, but the Xiangshan story will play out for many years. ®
Get our [19]Tech Resources
[1] https://m.weibo.cn/status/5119262297426864
[2] https://github.com/OpenXiangShan/XiangShan?tab=readme-ov-file
[3] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[4] https://www.theregister.com/2021/12/06/china_riscv/
[5] https://www.theregister.com/2023/06/23/red_hat_centos_move/
[6] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[7] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[8] https://regmedia.co.uk/2025/01/08/handout_kunminghu.jpg
[9] https://github.com/OpenXiangShan/XiangShan/blob/master/images/xs-arch-kunminghu.svg
[10] https://github.com/OpenXiangShan/XiangShan-doc/commit/e2d9cd6f0e779ff788630d34f1ef7ff106bb8f74
[11] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[12] https://www.theregister.com/2024/10/21/microsoft_arm_cobalt_100_cpu/
[13] https://www.theregister.com/2025/01/02/riscv_journey_to_mainstream/
[14] https://www.theregister.com/2024/12/04/riscv_ai_champion_investment/
[15] https://www.theregister.com/2024/10/28/tsmc_sophgo_huawei/
[16] https://www.theregister.com/2024/10/23/rva23_profile_ratified/
[17] https://spdx.org/licenses/MulanPSL-2.0.html
[18] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33Z35a1tJudNbAEDmQc2xWPQAAAAI&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[19] https://whitepapers.theregister.com/
"hasn’t progressed as quickly as hoped and argues that’s because developing high-end chips is hard."
Natalie Gritpants Jr
If you think that's hard, try verifying it. If you think verifying high-end chips is hard, try debugging a failing test
Xinchuang - "China 2025"
I applaud these efforts to produce a more performant RISC-V chip. I also admire the decision to publish the design.
It's the Chinese New Year at the end of January… and there's every chance we'll see new silicon and hardware announced, like the Roma 3 laptop.