Intel's Gelsinger talks up 'systems foundry' era of trillion-transistor chips
(2022/08/23)
- Reference: 1661265493
- News link: https://www.theregister.co.uk/2022/08/23/intels_gelsinger_hot_chips/
- Source link:
Hot Chips Intel CEO Pat Gelsinger sees a future where everything is a computer assembled from chiplets using advanced packaging technologies like Intel's own as the chipmaker seeks to keep Moore's Law alive.
Gelsinger was delivering a keynote from the annual [1]Hot Chips conference, running this year in virtual form. As you might expect, Intel still sees the future as revolving very much around its technology, and now that means assembling systems from multiple chiplets, as in its upcoming [2]Sapphire Rapids Xeon Scalable CPUs.
According to Gelsinger, this move marks a transition from the wafer foundry era to what he calls the systems foundry era, which will be delivered by a combination of wafer, packaging, chiplet, and software advances.
[3]
"If you think about it, the rack is becoming a system. And the system is becoming an advanced package of multiple dies and chiplets. Literally, the system is becoming the advanced packaging technology of the future," he said.
[4]
"And when I say the rack is becoming a system, the system is becoming an advanced chiplet-based SOP (system on package), that's exactly what we mean and how we see it evolving."
The drivers behind this are that customers don't just want more chips, they want more powerful chips, because AI models are getting larger and data volumes are getting bigger, and Intel expects we will reach a trillion transistors in a chip by 2030.
[5]
[6]
"Today, there are about 100 billion transistors on a package, and we see our way clear to getting to a trillion transistors by the end of the decade," Gelsinger said, adding: "With ribbon FET we have a fundamental new transistor structure that we're just about to come into, that we believe continues to scale through the end of the decade."
Ribbon FET is Intel's version of the [7]Gate-All-Around (GAA) transistor architecture, where the gate material wraps entirely around the conducting channel.
[8]
The way to deliver larger and more powerful systems is to build them out of smaller functions, according to Gelsinger, to deliver "customized heterogenous capabilities," and this is where 2D and 3D packaging technology comes in to give architects and designers the tools to "apply the right transistor for the right problems."
What Gelsinger is getting at here is that individual chiplets can be manufactured using whatever process node is most appropriate for power functions, RF capabilities, logic, and memory, and assembled together using advanced packaging technologies to build the complete chip.
[9]This tiny Intel Xeon-toting PC board can take your Raspberry Pi any day
[10]Intel hands over nearly 5,000 patents in deal with IP management outfit
[11]Intel finally takes the hint on software optimization
[12]Intel ups protection against physical chip attacks in Alder Lake
"And we have our next-generation capability to take advantage of these in products like [13]Meteor Lake , which are being brought to the marketplace next year. And beyond that Arrow Lake and our second gen of 3D packaging technologies, they're starting to take advantage of these types of advanced packaging capabilities," Gelsinger said.
However, a key part in all this will be standardizing how all the pieces fit together, and Gelsinger was again blowing Intel's trumpet here in mentioning its efforts in driving development behind the [14]Universal Chiplet Interconnect Express (UCIe) as an industry standard for die-to-die interconnects, based on the PCIe standard.
[15]
UCIe will make it possible to build a chip using different parts from different vendors, according to Gelsinger.
"You may say, hey, I'm getting two chiplets from Intel, I'm getting one of the chiplets from a TSMC factory, maybe the power supply components from TI, maybe there's an IO component coming from Global Foundries, and of course, Intel has the best packaging technologies so they're gonna be the one assembling all those chiplets together, but maybe it's another assembly provider as well, so we do see that mix and match happening," he said.
[16]
But you can't have an Intel keynote without mentioning Moore's Law, and Gelsinger said that all these advances are built on the continuation of Moore's Law.
"Moore's Law, this continuing doubling of transistor capability as the dimensions shrink over time, is fundamentally the driver of everything that we've been able to accomplish," he said, and promised that Intel will "keep moving Moore's Law forward." ®
Get our [17]Tech Resources
[1] https://hotchips.org/
[2] https://www.theregister.com/2022/06/08/intel_sapphire_rapids_delay/
[3] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YwT5mbGzo0k2w6H68s3GUQAAAI4&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[4] https://regmedia.co.uk/2022/08/23/intel4b.jpg
[5] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YwT5mbGzo0k2w6H68s3GUQAAAI4&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[6] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YwT5mbGzo0k2w6H68s3GUQAAAI4&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[7] https://www.theregister.com/2022/06/30/samsung_3nm_chips/
[8] https://regmedia.co.uk/2022/08/23/intel5b.jpg
[9] https://www.theregister.com/2022/08/16/intel_asus_singleboard/
[10] https://www.theregister.com/2022/08/15/intel_patents_tahoe_research/
[11] https://www.theregister.com/2022/08/13/intel_software_focus/
[12] https://www.theregister.com/2022/08/12/intel_ups_protection_against_chip/
[13] https://www.theregister.com/2022/02/18/intel_gelsinger_plan/
[14] https://www.theregister.com/2022/03/03/nvidia_apple_intel_ucie/
[15] https://regmedia.co.uk/2022/08/23/intel9b.jpg
[16] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YwT5mbGzo0k2w6H68s3GUQAAAI4&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[17] https://whitepapers.theregister.com/
Gelsinger was delivering a keynote from the annual [1]Hot Chips conference, running this year in virtual form. As you might expect, Intel still sees the future as revolving very much around its technology, and now that means assembling systems from multiple chiplets, as in its upcoming [2]Sapphire Rapids Xeon Scalable CPUs.
According to Gelsinger, this move marks a transition from the wafer foundry era to what he calls the systems foundry era, which will be delivered by a combination of wafer, packaging, chiplet, and software advances.
[3]
"If you think about it, the rack is becoming a system. And the system is becoming an advanced package of multiple dies and chiplets. Literally, the system is becoming the advanced packaging technology of the future," he said.
[4]
"And when I say the rack is becoming a system, the system is becoming an advanced chiplet-based SOP (system on package), that's exactly what we mean and how we see it evolving."
The drivers behind this are that customers don't just want more chips, they want more powerful chips, because AI models are getting larger and data volumes are getting bigger, and Intel expects we will reach a trillion transistors in a chip by 2030.
[5]
[6]
"Today, there are about 100 billion transistors on a package, and we see our way clear to getting to a trillion transistors by the end of the decade," Gelsinger said, adding: "With ribbon FET we have a fundamental new transistor structure that we're just about to come into, that we believe continues to scale through the end of the decade."
Ribbon FET is Intel's version of the [7]Gate-All-Around (GAA) transistor architecture, where the gate material wraps entirely around the conducting channel.
[8]
The way to deliver larger and more powerful systems is to build them out of smaller functions, according to Gelsinger, to deliver "customized heterogenous capabilities," and this is where 2D and 3D packaging technology comes in to give architects and designers the tools to "apply the right transistor for the right problems."
What Gelsinger is getting at here is that individual chiplets can be manufactured using whatever process node is most appropriate for power functions, RF capabilities, logic, and memory, and assembled together using advanced packaging technologies to build the complete chip.
[9]This tiny Intel Xeon-toting PC board can take your Raspberry Pi any day
[10]Intel hands over nearly 5,000 patents in deal with IP management outfit
[11]Intel finally takes the hint on software optimization
[12]Intel ups protection against physical chip attacks in Alder Lake
"And we have our next-generation capability to take advantage of these in products like [13]Meteor Lake , which are being brought to the marketplace next year. And beyond that Arrow Lake and our second gen of 3D packaging technologies, they're starting to take advantage of these types of advanced packaging capabilities," Gelsinger said.
However, a key part in all this will be standardizing how all the pieces fit together, and Gelsinger was again blowing Intel's trumpet here in mentioning its efforts in driving development behind the [14]Universal Chiplet Interconnect Express (UCIe) as an industry standard for die-to-die interconnects, based on the PCIe standard.
[15]
UCIe will make it possible to build a chip using different parts from different vendors, according to Gelsinger.
"You may say, hey, I'm getting two chiplets from Intel, I'm getting one of the chiplets from a TSMC factory, maybe the power supply components from TI, maybe there's an IO component coming from Global Foundries, and of course, Intel has the best packaging technologies so they're gonna be the one assembling all those chiplets together, but maybe it's another assembly provider as well, so we do see that mix and match happening," he said.
[16]
But you can't have an Intel keynote without mentioning Moore's Law, and Gelsinger said that all these advances are built on the continuation of Moore's Law.
"Moore's Law, this continuing doubling of transistor capability as the dimensions shrink over time, is fundamentally the driver of everything that we've been able to accomplish," he said, and promised that Intel will "keep moving Moore's Law forward." ®
Get our [17]Tech Resources
[1] https://hotchips.org/
[2] https://www.theregister.com/2022/06/08/intel_sapphire_rapids_delay/
[3] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YwT5mbGzo0k2w6H68s3GUQAAAI4&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[4] https://regmedia.co.uk/2022/08/23/intel4b.jpg
[5] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YwT5mbGzo0k2w6H68s3GUQAAAI4&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[6] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YwT5mbGzo0k2w6H68s3GUQAAAI4&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[7] https://www.theregister.com/2022/06/30/samsung_3nm_chips/
[8] https://regmedia.co.uk/2022/08/23/intel5b.jpg
[9] https://www.theregister.com/2022/08/16/intel_asus_singleboard/
[10] https://www.theregister.com/2022/08/15/intel_patents_tahoe_research/
[11] https://www.theregister.com/2022/08/13/intel_software_focus/
[12] https://www.theregister.com/2022/08/12/intel_ups_protection_against_chip/
[13] https://www.theregister.com/2022/02/18/intel_gelsinger_plan/
[14] https://www.theregister.com/2022/03/03/nvidia_apple_intel_ucie/
[15] https://regmedia.co.uk/2022/08/23/intel9b.jpg
[16] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YwT5mbGzo0k2w6H68s3GUQAAAI4&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[17] https://whitepapers.theregister.com/
Heating
It's interesting that Pat has not found a career in building heating systems.
A PC with an Intel processor can heat an entire room during the winter.