IBM wants to simplify 3D stacked chip manufacturing
(2022/07/08)
- Reference: 1657282511
- News link: https://www.theregister.co.uk/2022/07/08/ibm_3d_chips/
- Source link:
IBM says it has come up with a process that will make it easier to make 3D stacked chips, although can't confirm when this technology might be ready.
Big Blue has been working with Japanese semiconductor outfit [1]Tokyo Electron on a way to simplify the process of making 3D stacked chips. The pair say they have built a beta system in Albany, New York (presumably at the Thomas J Watson Research Center), where they will test how the process can be implemented into a full semiconductor manufacturing workflow to deliver a complete 3D chip stack.
Chip stacking is used mostly in products such as [2]high-bandwidth memory , but IBM believes it has the potential to side-step the [3]end of Moore's Law by expanding the number of transistors that can fit in a given volume rather than in a flat area spread out on a single chip.
[4]
The end of Moore's Law, as most Reg readers know, chiefly refers to the way manufacturing processes are potentially approaching the physical limits of silicon, with [5]2nm process nodes expected to come online within the next few years.
[6]Inspur hot on liquid-cooled servers as part of quest for carbon neutrality
[7]Micron releases DDR5 DRAM ready for next-gen servers
[8]Nexperia talks up its investment in UK wafer fab, says no plans to close
[9]Semiconductor market to be hit by fresh wave of rising component costs
Manufacturing vertically stacked chips requires fragile silicon wafers be attached to a carrier wafer during the production process. These carrier wafers can be also made of silicon, but mechanical force is needed to separate them after processing, which can damage the wafers and reduce yields, according to IBM. For this reason, glass is typically used, as it can be temporarily bonded to the production wafer and debonded using ultraviolet lasers.
IBM and Tokyo Electron say they have developed a new process that uses an infrared laser that can debond silicon, meaning that standard silicon wafers can be used as carriers instead of glass. This simplifies the production process by doing away with the need for glass, but is also claimed to have other advantages such as eliminating tool compatibility issues, reducing defects, and enabling inline testing of wafers.
[10]
The two companies have worked on this technology since 2018, as part of their collaboration on chip manufacturing that dates back more than 20 years. Tokyo Electron has largely been responsible for developing a new 300mm production unit capable of releasing and separating bonded silicon wafer pairs for volume manufacturing.
We asked IBM when this new process might actually be ready to deliver production 3D stacked chips, but they were not immediately able to respond. However, it seems likely that it will be at least several years before the test system translates into a usable commercial process, if at all. ®
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[1] https://www.tel.com/
[2] https://www.theregister.com/2021/10/20/sk_hynix_hbm3/
[3] https://www.theregister.com/2021/08/05/moores_law_what_next/
[4] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YshUpopTRlSye9ZC3IxmHAAAAJQ&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[5] https://www.theregister.com/2022/06/17/tsmc_details_2nm_node_using/
[6] https://www.theregister.com/2022/07/07/inspur_liquid_cooling/
[7] https://www.theregister.com/2022/07/07/micron_ddr5_dram/
[8] https://www.theregister.com/2022/07/06/nexperia_no_plans_close/
[9] https://www.theregister.com/2022/07/05/chip_market_supply_crunch/
[10] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YshUpopTRlSye9ZC3IxmHAAAAJQ&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[11] https://whitepapers.theregister.com/
Big Blue has been working with Japanese semiconductor outfit [1]Tokyo Electron on a way to simplify the process of making 3D stacked chips. The pair say they have built a beta system in Albany, New York (presumably at the Thomas J Watson Research Center), where they will test how the process can be implemented into a full semiconductor manufacturing workflow to deliver a complete 3D chip stack.
Chip stacking is used mostly in products such as [2]high-bandwidth memory , but IBM believes it has the potential to side-step the [3]end of Moore's Law by expanding the number of transistors that can fit in a given volume rather than in a flat area spread out on a single chip.
[4]
The end of Moore's Law, as most Reg readers know, chiefly refers to the way manufacturing processes are potentially approaching the physical limits of silicon, with [5]2nm process nodes expected to come online within the next few years.
[6]Inspur hot on liquid-cooled servers as part of quest for carbon neutrality
[7]Micron releases DDR5 DRAM ready for next-gen servers
[8]Nexperia talks up its investment in UK wafer fab, says no plans to close
[9]Semiconductor market to be hit by fresh wave of rising component costs
Manufacturing vertically stacked chips requires fragile silicon wafers be attached to a carrier wafer during the production process. These carrier wafers can be also made of silicon, but mechanical force is needed to separate them after processing, which can damage the wafers and reduce yields, according to IBM. For this reason, glass is typically used, as it can be temporarily bonded to the production wafer and debonded using ultraviolet lasers.
IBM and Tokyo Electron say they have developed a new process that uses an infrared laser that can debond silicon, meaning that standard silicon wafers can be used as carriers instead of glass. This simplifies the production process by doing away with the need for glass, but is also claimed to have other advantages such as eliminating tool compatibility issues, reducing defects, and enabling inline testing of wafers.
[10]
The two companies have worked on this technology since 2018, as part of their collaboration on chip manufacturing that dates back more than 20 years. Tokyo Electron has largely been responsible for developing a new 300mm production unit capable of releasing and separating bonded silicon wafer pairs for volume manufacturing.
We asked IBM when this new process might actually be ready to deliver production 3D stacked chips, but they were not immediately able to respond. However, it seems likely that it will be at least several years before the test system translates into a usable commercial process, if at all. ®
Get our [11]Tech Resources
[1] https://www.tel.com/
[2] https://www.theregister.com/2021/10/20/sk_hynix_hbm3/
[3] https://www.theregister.com/2021/08/05/moores_law_what_next/
[4] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YshUpopTRlSye9ZC3IxmHAAAAJQ&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[5] https://www.theregister.com/2022/06/17/tsmc_details_2nm_node_using/
[6] https://www.theregister.com/2022/07/07/inspur_liquid_cooling/
[7] https://www.theregister.com/2022/07/07/micron_ddr5_dram/
[8] https://www.theregister.com/2022/07/06/nexperia_no_plans_close/
[9] https://www.theregister.com/2022/07/05/chip_market_supply_crunch/
[10] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YshUpopTRlSye9ZC3IxmHAAAAJQ&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[11] https://whitepapers.theregister.com/
Anonymous Coward
There is single core performance and total capacity of the machine the core is in. Both are "performance", it just depends on what you need for your application.
I think we need to separate out Moore's Law and performance.
Until around a decade ago, the increase in transistors & density definitely improved performance.
But although we're still getting more transisters, we're just getting more cores & cache. (And complex instructions) Performance is increasing, but at a much, much slower rate.