RISC-V International emits more open CPU specs
(2022/06/22)
- Reference: 1655924406
- News link: https://www.theregister.co.uk/2022/06/22/riscv_latest_specifications/
- Source link:
Embedded World RISC-V International has grown its pile of royalty-free, open specifications, with additional documents covering firmware, hypervisors, and more.
[1]RISC-V – pronounced "risk five", and not to be confused with the other architecture of that name, [2]RISC-5 – essentially sets out how a CPU core should work from a software point of view. Chip designers can implement these instruction set specifications in silicon, and there are a good number of big industry players [3]backing it.
The latest [4]specs lay out four features that compatible processors should adhere to. Two of them, E-Trace and Zmmul, will be useful for organizations building RISC-V hardware and software, and the other two could prove important in future, aiding the development of OSes to run on RISC-V computers.
If you wanna make your own open-source chip, just Google it. Literally. Web giant says it'll fab them for free [5]READ MORE
One of these is the [6]UEFI boot protocol that specifies how system firmware obtains and handles information about the hardware before loading an OS kernel. Another defines a [7]Supervisor Binary Interface (SBI) between the hardware and an operating system or hypervisor kernel, complete with a reference implementation by Western Digital called [8]OpenSBI .
RISC-V International CTO Mark Himelstein said this was a "critical resource," offering "the ability to port supervisor-mode software across all RISC-V implementations, essentially allowing developers to write something once and apply it everywhere."
[9]
As for the others, the E-Trace specification allows for efficient processor-branch tracing on RISC-V devices. If that's your sort of jam, there's a 100+ page PDF on [10]GitHub .
[11]
[12]
The Zmmul extension specifies multiplication math support, with no division, primarily for small and simple embedded cores – there are already separate extensions for integer and floating-point math, including multiplication and division, for general-purpose application CPU cores.
(Historical RISC-y side note: the original Acorn ARM1 processor didn't have hardware for either multiplication or division, but it did have a [13]barrel shifter .)
[14]
The RISC-V instruction set architecture is still in its very early days, and as some at The Reg have opined before, [15]its future success remains far from certain. There isn't much general-purpose end-user RISC-V hardware out there that you can buy and try yourself, or fire up an emulator like Qemu.
[16]Will this be one of the world's first RISC-V laptops?
[17]The 'substantial contributions' Intel has promised to boost RISC-V adoption
[18]RISC-V needs more than an open architecture to compete
[19]MIPS discloses first RISC-V chips coming in Q4 2022
One of the few examples is the optional RISC-V processor module for the [20]ClockworkPi DevTerm . One of the first reviews of the RISC-V version is on [21]former TenFourFox browser maintainer Cameron Kaiser's blog [22]TalosSpace , and while he likes the device a lot, the review is very negative about the performance of the machine's Allwinner single-core system-on-chip.
For now, RISC-V presents no real threat to anyone on the higher-end mainstream general-purpose CPU performance front. Apple has [23]showed that investing a lot of time and money in making a large-scale highly integrated Arm SoC was thoroughly worth it, whether measured in raw performance, or performance per Watt, or price:performance. Now, the rest of the Arm industry has to catch up with Apple, while RISC-V still has to try to catch up with Arm.
Saying that, back in the day at least, the Arm world was a Silicon Wild West with every chip different, and it took a lot of industry effort and cooperation to, in some areas, standardize on things like firmware and the boot process. It's [24]why a project like Armbian emerged. Kudos to RISC-V International for realizing that and tackling this at an early stage. ®
Bootnote
The RISC-V name comes from it being the fifth generation of the original [25]Berkeley RISC design. The RISC-I chip had 78 registers, but its performance was disappointing (see the unusually discursive Wikipedia [26]article before someone deletes it). Nonetheless, it inspired Sun's original SPARC processor.
RISC-II had a remarkable 138 registers. RISC-III was the [27]SOAR CPU (Smalltalk On A RISC), and [28]RISC-IV the processor for SPUR (Symbolic Processing Using RISCs), a very early parallel-processor [29]workstation .
Get our [30]Tech Resources
[1] https://riscv.org/about/
[2] https://riskfive.com/
[3] https://riscv.org/membership/founding-members/
[4] https://riscv.org/announcements/2022/06/risc-v-announces-first-new-specifications-of-2022-adding-to-16-ratified-in-2021-risc-v-international/
[5] https://www.theregister.com/2020/07/03/open_chip_hardware/
[6] https://github.com/riscv-non-isa/riscv-uefi
[7] https://github.com/riscv-non-isa/riscv-sbi-doc
[8] https://github.com/riscv-software-src/opensbi
[9] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YrORBD4e5j41-k@gPj@evQAAAMM&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[10] https://github.com/riscv-non-isa/riscv-trace-spec/blob/main/riscv-trace-spec.pdf
[11] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YrORBD4e5j41-k@gPj@evQAAAMM&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[12] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YrORBD4e5j41-k@gPj@evQAAAMM&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[13] https://www.d.umn.edu/~gshute/logic/barrel-shifter.xhtml
[14] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YrORBD4e5j41-k@gPj@evQAAAMM&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[15] https://www.theregister.com/2022/05/16/riscv_world_domination/
[16] https://www.theregister.com/2022/05/18/first_riscv_laptop/
[17] https://www.theregister.com/2022/05/17/intel_riscv_contributions/
[18] https://www.theregister.com/2022/05/16/riscv_world_domination/
[19] https://www.theregister.com/2022/05/11/mips_riscv_chips/
[20] https://www.clockworkpi.com/devterm
[21] https://www.theregister.com/2021/03/31/tenfourfox_dev_quits/
[22] https://www.talospace.com/2022/05/mini-review-clockwork-pi-devterm-r-01.html
[23] https://www.theregister.com/2022/06/10/apples_m2_chip/
[24] https://www.theregister.com/2022/03/03/armbian_project_releases_version_2202/
[25] https://www2.eecs.berkeley.edu/Pubs/TechRpts/1982/5449.html
[26] https://en.wikipedia.org/wiki/Berkeley_RISC
[27] https://www2.eecs.berkeley.edu/Pubs/TechRpts/1985/5940.html
[28] https://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/6156.html
[29] https://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/6083.html
[30] https://whitepapers.theregister.com/
[1]RISC-V – pronounced "risk five", and not to be confused with the other architecture of that name, [2]RISC-5 – essentially sets out how a CPU core should work from a software point of view. Chip designers can implement these instruction set specifications in silicon, and there are a good number of big industry players [3]backing it.
The latest [4]specs lay out four features that compatible processors should adhere to. Two of them, E-Trace and Zmmul, will be useful for organizations building RISC-V hardware and software, and the other two could prove important in future, aiding the development of OSes to run on RISC-V computers.
If you wanna make your own open-source chip, just Google it. Literally. Web giant says it'll fab them for free [5]READ MORE
One of these is the [6]UEFI boot protocol that specifies how system firmware obtains and handles information about the hardware before loading an OS kernel. Another defines a [7]Supervisor Binary Interface (SBI) between the hardware and an operating system or hypervisor kernel, complete with a reference implementation by Western Digital called [8]OpenSBI .
RISC-V International CTO Mark Himelstein said this was a "critical resource," offering "the ability to port supervisor-mode software across all RISC-V implementations, essentially allowing developers to write something once and apply it everywhere."
[9]
As for the others, the E-Trace specification allows for efficient processor-branch tracing on RISC-V devices. If that's your sort of jam, there's a 100+ page PDF on [10]GitHub .
[11]
[12]
The Zmmul extension specifies multiplication math support, with no division, primarily for small and simple embedded cores – there are already separate extensions for integer and floating-point math, including multiplication and division, for general-purpose application CPU cores.
(Historical RISC-y side note: the original Acorn ARM1 processor didn't have hardware for either multiplication or division, but it did have a [13]barrel shifter .)
[14]
The RISC-V instruction set architecture is still in its very early days, and as some at The Reg have opined before, [15]its future success remains far from certain. There isn't much general-purpose end-user RISC-V hardware out there that you can buy and try yourself, or fire up an emulator like Qemu.
[16]Will this be one of the world's first RISC-V laptops?
[17]The 'substantial contributions' Intel has promised to boost RISC-V adoption
[18]RISC-V needs more than an open architecture to compete
[19]MIPS discloses first RISC-V chips coming in Q4 2022
One of the few examples is the optional RISC-V processor module for the [20]ClockworkPi DevTerm . One of the first reviews of the RISC-V version is on [21]former TenFourFox browser maintainer Cameron Kaiser's blog [22]TalosSpace , and while he likes the device a lot, the review is very negative about the performance of the machine's Allwinner single-core system-on-chip.
For now, RISC-V presents no real threat to anyone on the higher-end mainstream general-purpose CPU performance front. Apple has [23]showed that investing a lot of time and money in making a large-scale highly integrated Arm SoC was thoroughly worth it, whether measured in raw performance, or performance per Watt, or price:performance. Now, the rest of the Arm industry has to catch up with Apple, while RISC-V still has to try to catch up with Arm.
Saying that, back in the day at least, the Arm world was a Silicon Wild West with every chip different, and it took a lot of industry effort and cooperation to, in some areas, standardize on things like firmware and the boot process. It's [24]why a project like Armbian emerged. Kudos to RISC-V International for realizing that and tackling this at an early stage. ®
Bootnote
The RISC-V name comes from it being the fifth generation of the original [25]Berkeley RISC design. The RISC-I chip had 78 registers, but its performance was disappointing (see the unusually discursive Wikipedia [26]article before someone deletes it). Nonetheless, it inspired Sun's original SPARC processor.
RISC-II had a remarkable 138 registers. RISC-III was the [27]SOAR CPU (Smalltalk On A RISC), and [28]RISC-IV the processor for SPUR (Symbolic Processing Using RISCs), a very early parallel-processor [29]workstation .
Get our [30]Tech Resources
[1] https://riscv.org/about/
[2] https://riskfive.com/
[3] https://riscv.org/membership/founding-members/
[4] https://riscv.org/announcements/2022/06/risc-v-announces-first-new-specifications-of-2022-adding-to-16-ratified-in-2021-risc-v-international/
[5] https://www.theregister.com/2020/07/03/open_chip_hardware/
[6] https://github.com/riscv-non-isa/riscv-uefi
[7] https://github.com/riscv-non-isa/riscv-sbi-doc
[8] https://github.com/riscv-software-src/opensbi
[9] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YrORBD4e5j41-k@gPj@evQAAAMM&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[10] https://github.com/riscv-non-isa/riscv-trace-spec/blob/main/riscv-trace-spec.pdf
[11] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YrORBD4e5j41-k@gPj@evQAAAMM&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[12] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YrORBD4e5j41-k@gPj@evQAAAMM&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[13] https://www.d.umn.edu/~gshute/logic/barrel-shifter.xhtml
[14] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/systems&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YrORBD4e5j41-k@gPj@evQAAAMM&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[15] https://www.theregister.com/2022/05/16/riscv_world_domination/
[16] https://www.theregister.com/2022/05/18/first_riscv_laptop/
[17] https://www.theregister.com/2022/05/17/intel_riscv_contributions/
[18] https://www.theregister.com/2022/05/16/riscv_world_domination/
[19] https://www.theregister.com/2022/05/11/mips_riscv_chips/
[20] https://www.clockworkpi.com/devterm
[21] https://www.theregister.com/2021/03/31/tenfourfox_dev_quits/
[22] https://www.talospace.com/2022/05/mini-review-clockwork-pi-devterm-r-01.html
[23] https://www.theregister.com/2022/06/10/apples_m2_chip/
[24] https://www.theregister.com/2022/03/03/armbian_project_releases_version_2202/
[25] https://www2.eecs.berkeley.edu/Pubs/TechRpts/1982/5449.html
[26] https://en.wikipedia.org/wiki/Berkeley_RISC
[27] https://www2.eecs.berkeley.edu/Pubs/TechRpts/1985/5940.html
[28] https://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/6156.html
[29] https://www2.eecs.berkeley.edu/Pubs/TechRpts/1986/6083.html
[30] https://whitepapers.theregister.com/
Finally a potential brake on the general computing apocalypse we're sleep walking into with the way M$ is abusing UEFI