Europe completes first phase of silicon independence project
(2021/12/24)
- Reference: 1640332811
- News link: https://www.theregister.co.uk/2021/12/24/european_processor_initiative_phase_one_concludes/
- Source link:
The European Processor Initiative (EPI) has concluded the first phase of its efforts to create made-in-Europe chips, an effort it is hoped will reduce reliance on imports, improve sovereign capabilities, and create the continent's first exascale supercomputer.
The EPI’s end-of-year [1]report , published this week, notes a few major achievements, among them delivering the specification of “Rhea”, the first generation of the EPI General-Purpose Processor (GPP) implementation and its future derivates.
Rhea is built on Arm’s Neoverse V1 processor architecture, but it also has 29 RISC-V cores deployed as controllers. Rhea is planned to be deployed in an exascale super in 2023.
[2]
The chip was designed by French company SiPearl, which partnered with Atos to design the silicon.
[3]
[4]
SiPearl CEO Philippe Notton told The Register , in October 2021, that the Intel's upcoming Ponte Vecchio GPU accelerator will be paired with its Rhea chips in supercomputers.
The use of open-source instruction-set architectures ensures freedom from proprietary licences and export restrictions
Rhea will also use a RISC-V power controller developed by the University of Bologna and ETH Zurich. The controller uses "advanced control and artificial intelligence algorithms for the power management of large-scale systems-on-chips," according to EPI.
Another Phase One achievement was work on security IP that provides advanced, common-criteria certified, sovereign security IP for HPC and edge processors. One output of this effort is a “crypto tile” for integration into other open silicon.
Development of the European Processor Accelerator (EPAC) test chip proof of concept was another Phase One achievement.
[5]
Barcelona Supercomputing Center and Croatia-based University of Zagreb developed vector processing units for high-performance, low-power computing. It is based on Barcelona-based [6]Semidynamics’ Avispado RISC-V core .
The project also delivered a proof of concept for an innovative embedded high-performance compute platform and associated software development kit for the automotive market.
[7]National Cyber Strategy will lead to BritChip for mobile devices by 2025, claims UK.gov
[8]India makes $10B bid to grow local semiconductor industry to serve – and challenge – the world
[9]China's road to homegrown chip glory looks to be going for a RISC-V future
Most of the EPI’s work is done on the RISC-V architecture, often referred to as the Linux of chips with engineers collaborating to design, set and improve the architecture. It was created by researchers in 2010 and is free to license.
The architecture offers a modular design that allows developers to pick from extensions that add specialist vector processing, security and virtualization functionality.
"The use of open-source instruction-set architectures ensures freedom from proprietary licences and export restrictions," the EPI said, a nod to the fact that Arm and Intel make fine products, but are beholden to government regulation that can prevent their tech crossing borders.
[10]
The EPI has 28 partners collaborating on chip designs across 10 European countries. Phase one of the initiative had a budget of €79 million, with funds going to Europe-based startups, companies and researchers to develop chips.
It’s hoped the project strengthens local supply chains by building more fabs across the continent area, to develop sovereign capacity and to address the semiconductor shortage that has slowed production of devices ranging from cars to the [11]Raspberry Pi .
The EPI’s second phase, which starts next year, will focus on putting the chips developed in Phase One into production. ®
Get our [12]Tech Resources
[1] https://www.european-processor-initiative.eu/successful-conclusion-of-european-processor-initiative-phase-one
[2] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/front&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YcWoa5pfRHZvFfEfVrWmYwAAAQU&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
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[6] https://semidynamics.com/products/avispado
[7] https://www.theregister.com/2021/12/16/national_cyber_strategy_uk_launched/
[8] https://www.theregister.com/2021/12/16/india_semiconductor_mission/
[9] https://www.theregister.com/2021/12/09/china_homegrown_chips/
[10] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/front&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YcWoa5pfRHZvFfEfVrWmYwAAAQU&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[11] https://www.theregister.com/2021/12/20/raspberry_pi_delay/
[12] https://whitepapers.theregister.com/
The EPI’s end-of-year [1]report , published this week, notes a few major achievements, among them delivering the specification of “Rhea”, the first generation of the EPI General-Purpose Processor (GPP) implementation and its future derivates.
Rhea is built on Arm’s Neoverse V1 processor architecture, but it also has 29 RISC-V cores deployed as controllers. Rhea is planned to be deployed in an exascale super in 2023.
[2]
The chip was designed by French company SiPearl, which partnered with Atos to design the silicon.
[3]
[4]
SiPearl CEO Philippe Notton told The Register , in October 2021, that the Intel's upcoming Ponte Vecchio GPU accelerator will be paired with its Rhea chips in supercomputers.
The use of open-source instruction-set architectures ensures freedom from proprietary licences and export restrictions
Rhea will also use a RISC-V power controller developed by the University of Bologna and ETH Zurich. The controller uses "advanced control and artificial intelligence algorithms for the power management of large-scale systems-on-chips," according to EPI.
Another Phase One achievement was work on security IP that provides advanced, common-criteria certified, sovereign security IP for HPC and edge processors. One output of this effort is a “crypto tile” for integration into other open silicon.
Development of the European Processor Accelerator (EPAC) test chip proof of concept was another Phase One achievement.
[5]
Barcelona Supercomputing Center and Croatia-based University of Zagreb developed vector processing units for high-performance, low-power computing. It is based on Barcelona-based [6]Semidynamics’ Avispado RISC-V core .
The project also delivered a proof of concept for an innovative embedded high-performance compute platform and associated software development kit for the automotive market.
[7]National Cyber Strategy will lead to BritChip for mobile devices by 2025, claims UK.gov
[8]India makes $10B bid to grow local semiconductor industry to serve – and challenge – the world
[9]China's road to homegrown chip glory looks to be going for a RISC-V future
Most of the EPI’s work is done on the RISC-V architecture, often referred to as the Linux of chips with engineers collaborating to design, set and improve the architecture. It was created by researchers in 2010 and is free to license.
The architecture offers a modular design that allows developers to pick from extensions that add specialist vector processing, security and virtualization functionality.
"The use of open-source instruction-set architectures ensures freedom from proprietary licences and export restrictions," the EPI said, a nod to the fact that Arm and Intel make fine products, but are beholden to government regulation that can prevent their tech crossing borders.
[10]
The EPI has 28 partners collaborating on chip designs across 10 European countries. Phase one of the initiative had a budget of €79 million, with funds going to Europe-based startups, companies and researchers to develop chips.
It’s hoped the project strengthens local supply chains by building more fabs across the continent area, to develop sovereign capacity and to address the semiconductor shortage that has slowed production of devices ranging from cars to the [11]Raspberry Pi .
The EPI’s second phase, which starts next year, will focus on putting the chips developed in Phase One into production. ®
Get our [12]Tech Resources
[1] https://www.european-processor-initiative.eu/successful-conclusion-of-european-processor-initiative-phase-one
[2] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/front&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YcWoa5pfRHZvFfEfVrWmYwAAAQU&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[3] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/front&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YcWoa5pfRHZvFfEfVrWmYwAAAQU&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[4] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/front&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YcWoa5pfRHZvFfEfVrWmYwAAAQU&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[5] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/front&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YcWoa5pfRHZvFfEfVrWmYwAAAQU&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[6] https://semidynamics.com/products/avispado
[7] https://www.theregister.com/2021/12/16/national_cyber_strategy_uk_launched/
[8] https://www.theregister.com/2021/12/16/india_semiconductor_mission/
[9] https://www.theregister.com/2021/12/09/china_homegrown_chips/
[10] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/front&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YcWoa5pfRHZvFfEfVrWmYwAAAQU&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[11] https://www.theregister.com/2021/12/20/raspberry_pi_delay/
[12] https://whitepapers.theregister.com/
Re: "efforts to create made-in-Europe chips"
Clausewitz 4.0
Market is already fractured.
Chinese don't use Intel/AMD for high computing and National Security level stuff.
There are already four or five different plataforms, even more, you just don't know about them.
Re: "efforts to create made-in-Europe chips"
Warm Braw
There are two aspects to this: one is chip fabrication capability (which has nothing to do with ISAs), the other is design capability.
We're unlikely to see cutting edge fabs in Europe any time soon - the investment required is enormous simply as a form of insurance. However, the current crisis in vehicle manufacturing demonstrates there may well be an economic benefit in being able to produce more commodity components such as industrial microcontrollers.
There's clearly also some interest in increasing design skills and having input to newer initiatives like RISC-V. In the controller area it's more likely there'll be a convergence of instruction sets (on something like RISC-V) as opposed to the eclectic range we currently have. The EPI obviously has ambitions in high-performance computing, but that's going to be a somewhat bigger challenge.
Is this an EU or Europe thing ?
Anonymous Coward
As in where is the UK with this ?
Re: Is this an EU or Europe thing ?
Anonymous Coward
We probably aren't in there, processors don't work well when you put borders around your parts of the chip design and waste valuable silicon space decorating them with flags and royal insignia.
Re: Is this an EU or Europe thing ?
rjsmall
Wouldn't be the first time images have been etched on to silicon https://uk.pcmag.com/components/83424/cool-images-hidden-on-silicon-chips
"efforts to create made-in-Europe chips"
Interesting. Is this going to fracture the CPU market ? Are we going to find ourselves in a world where there's Intel, AMD and EuroChip ?
And what about other countries ramping up their own fabs ? Are we going to find a dozen choices for CPUs in the next decade, or is everyone simply going to make Intel or AMD designs ?
I'm not strongly against the idea, mind you, but choosing between the two incumbents is already a headache, I'd hate to think of having to choose between four or five different platforms.