RISC-V boffins lay out a plan for bringing the architecture to high-performance computing
- Reference: 1623349934
- News link: https://www.theregister.co.uk/2021/06/10/riscv_hpc/
- Source link:
For an architecture which only began life at the University of California, Berkeley, in 2010, RISC-V has enjoyed considerable success.
A wealth of products based on RISC-V are already in the market, with more arriving regularly, but the majority of these, like [1]Seagate's storage processor designs and the [2]OpenTitan root-of-trust (RoT) , target embedded or otherwise less performance-critical applications.
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RISC-V International, though, believes there are more strings to its bow. In [4]an announcement from member Dr John D Davis, chair of the RISC-V Special Interest Group on High Performance Computing (SIG-HPC), it has set out its stall for taking over the performance end of the market.
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"HPC is everywhere," claimed Davis. "The basic algorithms and kernels power a wide range of computations. It starts in the traditional space of supercomputers used for weather forecasting, computational fluid dynamics, to material science, and protein folding, in both research and industrial applications. We even see HPC in the cloud.
"The SIG-HPC aims to enable all of those workloads and more. As a result, there are 141 members on the mailing list and 10 active research, academia, and industrial members from a wide range of organisations and these are growing exponentially. The group is united in making RISC-V an option in HPC. It also works with other technical groups in RISC-V to make sure HPC requirements are kept in mind for the evolving ISA."
[7]Google says its artificial intelligence is faster and better than humans at laying out chips for artificial intelligence
[8]China's ISCAS to build 2,000 RISC-V laptops by the end of 2022 as nation seeks to cut reliance on Arm, Intel chips
[9]What links AMD CPU guru Jim Keller, an AI chip upstart, and SiFive? This vector-crunching 64-bit RISC-V processor
[10]DARPA adds RISC-V to its Toolbox: Defense researchers can get special access to SiFive chip designs
While not committing to a formal roadmap, merely confirming one is in the works, Davis has set out the goals the SIG-HPC is targeting for the year ahead – beginning with an effort to map the exiting HPC software ecosystem to RISC-V. "This," he explained, "involves automation to discover which open source software, from libraries to benchmarks and applications, work out-of-the-box on the RISC-V ISA.
"Overall, SIG-HPC's vision is that of a future where the entire HPC system can be based on open source components. Today's technology trends require specialisation to meet the power and performance workload targets. This enables hardware-software co-design, which is a natural fit for open systems, enabling more research and development. The next major milestone for SIG-HPC is to map the HPC ecosystem and develop an associated roadmap."
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It's not pie in the sky – back in 2019 Chinese tech giant Alibaba unveiled [12]high-performance 16-core RISC-V chips for its cloud business. These, however, are proprietary, closed-source designs enabled by the permissive licensing behind the free and open-source RISC-V ISA itself, but of little use to a community looking to further the HPC effort.
That's not to say others aren't working on more open designs. In India [13]the SHAKTI project , launched in 2014 by the Reconfigurable Intelligent Systems Engineering (RISE) Group of IIT-Madras, aims to produce open-source chip designs ranging from low-power E-Class parts for embedded machines up to H-Class for HPC – although [14]it's early days yet .
"It is a very interesting ambition of the RISC-V community, which highlights that RISC-V can be competitive even beyond embedded and single-board computers," commented Philipp Wagner, director at the nonprofit FOSSi Foundation, which aims to build a community and ecosystem of free and open-source silicon including but not limited to RISC-V.
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"There is a long road ahead, in particular for open-source silicon components to become integral parts of high-performance computing systems, and the creation of an enabling ecosystem is an important milestone."
In the meantime, SIG-HPC is actively soliciting new members to assist in its efforts. Interested parties can join the discussion list by [16]sending an email . ®
Get our [17]Tech Resources
[1] https://www.theregister.com/2020/12/08/seagate_risc_v_computational_storage/
[2] https://www.theregister.com/2019/11/05/google_opentitan_soc_riscv/
[3] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/hpc&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YMKLhjqKW5p-iF0QA2Ll8QAAANI&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[4] https://riscv.org/blog/2021/06/risc-v-sig-hpc-enabling-risc-v-in-hpc-supercomputers-to-the-edge-and-emerging-ai-ml-dl-hpc-workloads/
[5] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/hpc&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YMKLhjqKW5p-iF0QA2Ll8QAAANI&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[6] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/hpc&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YMKLhjqKW5p-iF0QA2Ll8QAAANI&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[7] https://www.theregister.com/2021/06/09/google_ai_chip_floorplans/
[8] https://www.theregister.com/2021/06/08/iscas_2000_riscv_laptops/
[9] https://www.theregister.com/2021/04/22/tenstorrent_sifive_intelligence_x280_licensed/
[10] https://www.theregister.com/2021/04/07/sifive_darpa_chips/
[11] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/hpc&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YMKLhjqKW5p-iF0QA2Ll8QAAANI&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[12] https://www.theregister.com/2019/07/27/alibaba_risc_v_chip/
[13] https://www.theregister.com/2020/08/19/india_microprocessor_challenge_risc_v/
[14] https://www.theregister.com/2020/09/24/shakti_moushik_cpu_india/
[15] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/hpc&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YMKLhjqKW5p-iF0QA2Ll8QAAANI&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[16] mailto:sig-hpc+subscribe@lists.riscv.org
[17] https://whitepapers.theregister.com/
Re: OpenRISC
The advantage of RISC-V over OpenRISC is that it has more momentum, more financial backing, more corporate and enthusiast interest, and (I'm pretty sure) more hardware available now or on the horizon. It's an Arm rival that seems to have gained traction.
OpenPOWER and OpenSPARC just seem out of reach. We do keep an eye out for them. I can imagine folks feel OP and OS are a little encumbered by their parents, IBM and Oracle, respectively.
Also, Intel just reportedly tried to buy a RISC-V startup for $2bn+. I don't see that happening with OR, OP, and OS outfits.
If there's a screw-up in the RISC-V world, then let us know if we don't spot it, and we'll write about it. We're pro-competition and we like tracking things that may challenge the status quo (eg, Arm). RISC-V is still so young that it's not in widespread use and the opportunity for that community to blow it hasn't come up yet.
There may be some technical limitations to OpenRISC v RISC-V. The people who created RV complained that OR still had branch delay slots (ew), the architecture and its software stacks weren't fully 64-bit ready, and the ISA encoding space gave too much room to immediate values, which is awkward.
Sure, I hope one day we get a chance to do a technical look at RISC-V v OpenRISC v OpenPOWER v OpenSPARC, but for now, the reason why we write about RISC-V is because we like an underdog. As Arm's CEO said, RISC-V keeps Arm on its toes, which is good for everyone. OpenRISC and OpenPOWER ain't doing that.
C.
Has RiscV Got What Makes A Super Super?
I'm not convinced. What a supercomputer these days needs is SIMD cores closely coupled with fast memory interfaces and fast low latency interconnecting fabric. The CPU ISA that is used to orchistrate it all is comparatively unimportant, so long as it does not produce much heat itself.
So if RiscV wants to get into the HPC business, it'll need those things. And the problem is that getting software math kernels for SIMD cores right take a lot of very specialised care and expertise...
OpenRISC
So what advantages does any of this have over OpenRISC (open ISA & open reference design), OpenPOWER (open ISA, multiple reference designs based on older Power silicon) or OpenSPARC?
These glowing self-congratulatory pieces are getting somewhat tiresome, to be honest. Where's the journalism?