SK Hynix boss predicts CPUs and RAM will merge, chipmakers will hold hands to make it happen
(2021/03/23)
- Reference: 1616479329
- News link: https://www.theregister.co.uk/2021/03/23/seok_hee_lee_sk_hynix_predictions/
- Source link:
The CEO of SK Hynix, the world’s second-largest memory manufacturer behind Samsung, has tipped the merger of RAM and CPUs, and the rise of the Compute Express Link standard.
Delivering the keynote at the Institute of Electrical and Electronics Engineers’ International Reliability Physics Symposium (IRPS), CEO Seok-Hee Lee delivered his vision for the future of memory and the industries that rely on it.
[1]
“There will be a convergence of memory and logic,” he predicted. “The concept is to add a few computing functions of CPU to DRAM.”
“As the speed was increased in high-bandwidth memory by increasing the number of channels between the CPU and the memory, the speed will increase further in Processing Near Memory (PNM), where both the CPU and the memory exist within a single module.”
[2]
“The speed will further increase in Processing In Memory (PIM), where the CPU and the memory exists within a single package. Ultimately, speed will increase further in Computing in Memory(CIM), where the CPU and the memory is integrated within in a single die, to deliver high performance computing system.”
SK Hynix does not make CPUs and Lee didn’t even hint the company would do so.
So how can he predict that memory and compute will merge? Lee proposed cross-industry collaboration.
“In the era of fierce competition for miniaturization, the matters of technology completion and productivity were dealt with through vertical relations with suppliers,” he opened. “Now, however, is the time when various partners building the semiconductor industry ecosystem must form a cooperative partnership. Only by establishing a strategic partnership for Open Innovation based on collaboration and sharing with customers, suppliers, academia and government, we can shape a new era, which pursues both economic and social value.”
SK Hynix starts churning out 18GB LPDDR5 mobile memory chips – with ASUS first in line [3]READ MORE
SK Hynix’s [4]canned statement even defined “open innovation” as “a paradigm that assumes that firms can and should use external ideas and technology required and share the internal resources outside the firm to create a new product or a service.”
Which sounds like world in which a future server could have “Intel and SK Hynix Inside”. And also suggests that Apple is onto something with its M1 design that puts CPU, memory, and much more on the same die.
Lee was also bullish about the prospects of the [5]Compute Express Link standard , a cross-industry effort to move data quickly and efficiently between CPUs and accelerators such as GPUs and smart network interface cards.
“CXL memory is being prepared as a solution that not only expands bandwidth and capacity but also realizes the value of a persistent memory,” Lee said in his speech. “I believe this will become a solution to narrow the gap between the memory performance and the industry requirements,” he said.
Much of Lee’s speech was devoted to necessary breakthroughs in chipmaking tech that Lee said SK Hynix will deliver in order to build faster, higher-capacity memory.
A sample: “We are improving materials and design structures for technical evolution in each field of DRAM and NAND, and solving the reliability problems step by step. If the platform is innovated successfully based on this, it is possible to achieve the DRAM process below 10 nanometers (nm) and stack over 600 layers of NAND in the future.”
As SK Hynix’s current best effort is 176-layer NAND, storage density looks set to improve markedly.
Lee’s speech can be viewed below. ®
[6]
[7]YouTube Video
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[3] https://www.theregister.com/2021/03/08/sk_hynix_lpddr5/
[4] https://news.skhynix.com/sk-hynix-ceo-seok-hee-lee-talks-about-the-future-of-memory-semiconductor-and-sk-hynixs-management-strategy/
[5] https://www.theregister.com/2020/11/10/compute_express_link_spec_hits/
[6] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/storage&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YFnKUczW3VQD5BJ5t13PfQAAABY&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[7] https://www.youtube.com/watch?v=uldHpwtmFLY&t=593s
[8] https://whitepapers.theregister.com/
Delivering the keynote at the Institute of Electrical and Electronics Engineers’ International Reliability Physics Symposium (IRPS), CEO Seok-Hee Lee delivered his vision for the future of memory and the industries that rely on it.
[1]
“There will be a convergence of memory and logic,” he predicted. “The concept is to add a few computing functions of CPU to DRAM.”
“As the speed was increased in high-bandwidth memory by increasing the number of channels between the CPU and the memory, the speed will increase further in Processing Near Memory (PNM), where both the CPU and the memory exist within a single module.”
[2]
“The speed will further increase in Processing In Memory (PIM), where the CPU and the memory exists within a single package. Ultimately, speed will increase further in Computing in Memory(CIM), where the CPU and the memory is integrated within in a single die, to deliver high performance computing system.”
SK Hynix does not make CPUs and Lee didn’t even hint the company would do so.
So how can he predict that memory and compute will merge? Lee proposed cross-industry collaboration.
“In the era of fierce competition for miniaturization, the matters of technology completion and productivity were dealt with through vertical relations with suppliers,” he opened. “Now, however, is the time when various partners building the semiconductor industry ecosystem must form a cooperative partnership. Only by establishing a strategic partnership for Open Innovation based on collaboration and sharing with customers, suppliers, academia and government, we can shape a new era, which pursues both economic and social value.”
SK Hynix starts churning out 18GB LPDDR5 mobile memory chips – with ASUS first in line [3]READ MORE
SK Hynix’s [4]canned statement even defined “open innovation” as “a paradigm that assumes that firms can and should use external ideas and technology required and share the internal resources outside the firm to create a new product or a service.”
Which sounds like world in which a future server could have “Intel and SK Hynix Inside”. And also suggests that Apple is onto something with its M1 design that puts CPU, memory, and much more on the same die.
Lee was also bullish about the prospects of the [5]Compute Express Link standard , a cross-industry effort to move data quickly and efficiently between CPUs and accelerators such as GPUs and smart network interface cards.
“CXL memory is being prepared as a solution that not only expands bandwidth and capacity but also realizes the value of a persistent memory,” Lee said in his speech. “I believe this will become a solution to narrow the gap between the memory performance and the industry requirements,” he said.
Much of Lee’s speech was devoted to necessary breakthroughs in chipmaking tech that Lee said SK Hynix will deliver in order to build faster, higher-capacity memory.
A sample: “We are improving materials and design structures for technical evolution in each field of DRAM and NAND, and solving the reliability problems step by step. If the platform is innovated successfully based on this, it is possible to achieve the DRAM process below 10 nanometers (nm) and stack over 600 layers of NAND in the future.”
As SK Hynix’s current best effort is 176-layer NAND, storage density looks set to improve markedly.
Lee’s speech can be viewed below. ®
[6]
[7]YouTube Video
Get our [8]Tech Resources
[1] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/storage&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2YFnKUczW3VQD5BJ5t13PfQAAABY&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[2] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/storage&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33YFnKUczW3VQD5BJ5t13PfQAAABY&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[3] https://www.theregister.com/2021/03/08/sk_hynix_lpddr5/
[4] https://news.skhynix.com/sk-hynix-ceo-seok-hee-lee-talks-about-the-future-of-memory-semiconductor-and-sk-hynixs-management-strategy/
[5] https://www.theregister.com/2020/11/10/compute_express_link_spec_hits/
[6] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_onprem/storage&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44YFnKUczW3VQD5BJ5t13PfQAAABY&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[7] https://www.youtube.com/watch?v=uldHpwtmFLY&t=593s
[8] https://whitepapers.theregister.com/
Transputer come to mind?
rtfazeberdee
parallel computing again?
Ultimately, speed will increase further in Computing in Memory(CIM)
Mike 137
Heat will increase too. Heat generation is a function of switching speed and there's an ultimate limit at which a single die can't dissipate heat fast enough to stay within safe temperature limits because heat generation is volumetric (the third power or cube) but dissipation is areal (the second power or square). This is well known - indeed a colleague wrote a PhD thesis on it in the mid-80s, and I think we're getting near that limit already.
Admittedly, there are a few use cases where blindingly fast hardware is necessary, but if we improved the currently appalling efficiency of code, it would reduce the need for raw hardware speed by quite a lot in most cases.
A Good Idea
Since a larger cache is one way to improve the performance of a CPU, having a wider-bandwidth pathway to memory would obviously bring benefits. Look at the innards of the NEC SX-9 supercomputer, which ties each of its CPUs directly to sixteen DRAM modules.
So not having to worry about pin count, not having to drive an external interface, would be greatly beneficial.
The problem, though, with going all the way to putting everything on a single die instead of just some type of module, the way HBM does already, is that die sizes are limited. Putting, say, eight cores and 16 gigabytes of DRAM on one die isn't likely to be possible for some time.
Of course, though, one thing chipmakers are looking for is a way to eliminate die size as a constraint. If you could have a multichip module where the connections between dies were essentially indistinguishable from on-die connections, imposing no additional delays or requirements for driviing, then, while major units like CPU cores would still have to be within a single die, cache and memory on other dies would be as good as on the same die.