IBM takes Power10 processors down to 7nm with Samsung, due to ship by end of 2021
(2020/08/17)
- Reference: 1597642325
- News link: https://www.theregister.co.uk/2020/08/17/ibm_t7nm_power10/
- Source link:
Hot Chips Big Blue hopes to roll out its first commercial 7nm data-center-grade processors – the IBM Power10 series – by the end of 2021.
Each Samsung-fabricated chip packs 18 billion transistors into a 602mm 2 die, and up to 15 cores that can be used for compute. Each CPU core can run up to eight threads simultaneously (SMT8). Each of these 64-bit processors sports up to 120MB of L3 cache plus support for PCIe 5 running up to 32GT/s, Open Memory Interface (OMI) running up to 1TB/s, and IBM's PowerAxon interconnect for adding OpenCAPI accelerators, IO, and more memory, again running up to 1TB/s.
Interestingly enough, there are 16 cores on the die. IBM distinguished engineer William Starke, who works on Power, told The Register : "As is the case for any large processor chip made by any vendor, the natural outcome of the manufacturing process results in different SKUs with varying core counts, with a limited fraction of all-core-good parts. Given the Power ecosystem's high demand for highest core-count offerings, it is economically best to provide a manufacturing spare, to vastly increase the percentage of highest core-count parts."
Every chip maker does so-called binning, based on defects and characteristics of the final dies, it's just interesting to see IBM hold one spare, so that the official specs say "up to 15" CPU cores rather than up to 16.
[1]
The Power10 processor's in-depth tech specs ... Click to enlarge. Credit: IBM
We're told Power10's core architecture focuses on accelerating matrix math operations for use in AI, and is designed with the needs of Red Hat's OpenShift in mind. It also features four times as many AES encryption engines compared to the Power9 family, provides hardware-level protections for containers running within virtual machines – so one bad container can't turn on its neighbors, apparently – and has built-in defenses to hopefully prevent data-leaking side-channel attacks.
It supports memory access within clusters of machines, allowing multiple petabytes of data in RAM to be shared via PowerAxon.
Power10 implements [2]Power ISA 3.1 , which was published in May. This [3]features so-called prefixed instructions that are eight bytes long, enabling things like a rather large PC-relative addressing ranges. There's also Bfloat16 support, byte reversing instructions, new vector instructions, 128-bit integer math operations, and more.
Power10 is more suited to inference rather than training, IBM pointed out. Training is intensive enough to require accelerators, such as GPUs and FPGAs.
[4]
New chip ... Power10 in all its glory. Click to enlarge. Source: IBM
Other upgrades include improved memory bandwidth, and more L2 cache memory, which means that each Power10 core has up to 30 per cent more performance than a Power9 sibling, IBM said. You can have up to 16 sockets in a single system, and up to 4TB per socket of OMI DRAM, depending on the configuration.
Power veep Steve Sibley told The Register IBM was aiming to ship Power10 chips to customers by Q4 of next year. Power10 is IBM's first Samsung-fabricated 7nm offering, and the pair of tech giants began collaborating in 2015 when IBM pledged $3bn in R&D toward next-gen Power processors.
“With POWER10 we’ve designed the premier processor for enterprise hybrid cloud, delivering the performance and security clients expect from IBM,” [5]said Stephen Leonard, GM of IBM Cognitive Systems. “With Red Hat OpenShift emerging as the default choice for hybrid cloud, IBM POWER10 brings hardware-based capacity and security enhancements for containers to the IT infrastructure level.”
You can find a selection of slides with more technical details on Power10, including the microarchitecture, from IBM [6]right here [PDF]. Big Blue is due to discuss its new designs at the now-virtual Hot Chips [7]conference today. ®
Get our [8]Tech Resources
[1] https://regmedia.co.uk/2020/08/15/power10slide.jpg
[2] https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0
[3] https://fuse.wikichip.org/news/3530/ibm-releases-power-isa-v3-1-to-present-power10-at-hot-chips-32/
[4] https://regmedia.co.uk/2020/08/15/power10.jpg
[5] https://newsroom.ibm.com/2020-08-17-IBM-Reveals-Next-Generation-IBM-POWER10-Processor
[6] https://regmedia.co.uk/2020/08/17/ibm_power10_summary.pdf
[7] https://www.hotchips.org/program/
[8] https://whitepapers.theregister.com/
Each Samsung-fabricated chip packs 18 billion transistors into a 602mm 2 die, and up to 15 cores that can be used for compute. Each CPU core can run up to eight threads simultaneously (SMT8). Each of these 64-bit processors sports up to 120MB of L3 cache plus support for PCIe 5 running up to 32GT/s, Open Memory Interface (OMI) running up to 1TB/s, and IBM's PowerAxon interconnect for adding OpenCAPI accelerators, IO, and more memory, again running up to 1TB/s.
Interestingly enough, there are 16 cores on the die. IBM distinguished engineer William Starke, who works on Power, told The Register : "As is the case for any large processor chip made by any vendor, the natural outcome of the manufacturing process results in different SKUs with varying core counts, with a limited fraction of all-core-good parts. Given the Power ecosystem's high demand for highest core-count offerings, it is economically best to provide a manufacturing spare, to vastly increase the percentage of highest core-count parts."
Every chip maker does so-called binning, based on defects and characteristics of the final dies, it's just interesting to see IBM hold one spare, so that the official specs say "up to 15" CPU cores rather than up to 16.
[1]
The Power10 processor's in-depth tech specs ... Click to enlarge. Credit: IBM
We're told Power10's core architecture focuses on accelerating matrix math operations for use in AI, and is designed with the needs of Red Hat's OpenShift in mind. It also features four times as many AES encryption engines compared to the Power9 family, provides hardware-level protections for containers running within virtual machines – so one bad container can't turn on its neighbors, apparently – and has built-in defenses to hopefully prevent data-leaking side-channel attacks.
It supports memory access within clusters of machines, allowing multiple petabytes of data in RAM to be shared via PowerAxon.
Power10 implements [2]Power ISA 3.1 , which was published in May. This [3]features so-called prefixed instructions that are eight bytes long, enabling things like a rather large PC-relative addressing ranges. There's also Bfloat16 support, byte reversing instructions, new vector instructions, 128-bit integer math operations, and more.
Power10 is more suited to inference rather than training, IBM pointed out. Training is intensive enough to require accelerators, such as GPUs and FPGAs.
[4]
New chip ... Power10 in all its glory. Click to enlarge. Source: IBM
Other upgrades include improved memory bandwidth, and more L2 cache memory, which means that each Power10 core has up to 30 per cent more performance than a Power9 sibling, IBM said. You can have up to 16 sockets in a single system, and up to 4TB per socket of OMI DRAM, depending on the configuration.
Power veep Steve Sibley told The Register IBM was aiming to ship Power10 chips to customers by Q4 of next year. Power10 is IBM's first Samsung-fabricated 7nm offering, and the pair of tech giants began collaborating in 2015 when IBM pledged $3bn in R&D toward next-gen Power processors.
“With POWER10 we’ve designed the premier processor for enterprise hybrid cloud, delivering the performance and security clients expect from IBM,” [5]said Stephen Leonard, GM of IBM Cognitive Systems. “With Red Hat OpenShift emerging as the default choice for hybrid cloud, IBM POWER10 brings hardware-based capacity and security enhancements for containers to the IT infrastructure level.”
You can find a selection of slides with more technical details on Power10, including the microarchitecture, from IBM [6]right here [PDF]. Big Blue is due to discuss its new designs at the now-virtual Hot Chips [7]conference today. ®
Get our [8]Tech Resources
[1] https://regmedia.co.uk/2020/08/15/power10slide.jpg
[2] https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0
[3] https://fuse.wikichip.org/news/3530/ibm-releases-power-isa-v3-1-to-present-power10-at-hot-chips-32/
[4] https://regmedia.co.uk/2020/08/15/power10.jpg
[5] https://newsroom.ibm.com/2020-08-17-IBM-Reveals-Next-Generation-IBM-POWER10-Processor
[6] https://regmedia.co.uk/2020/08/17/ibm_power10_summary.pdf
[7] https://www.hotchips.org/program/
[8] https://whitepapers.theregister.com/