GCC 17 Now Supports Using -mtune=native -mcpu=native On RISC-V
([RISC-V] 6 Hours Ago
-mtune=native -mcpu=native)
- Reference: 0001656254
- News link: https://www.phoronix.com/news/GCC-17-RISC-V-mtune-mcpu-native
- Source link:
As a follow up to last month's article about patches being posted for enabling "-mcpu=native -mtune=native" support for RISC-V with the GCC compiler, that code is now merged for what will become the GCC 17.1 release in the early months of 2027.
GCC until now has not supported "-mcpu=native -mtune=native" on RISC-V systems if wanting to target the code generation and tuning to the CPU detected in a given system. It's an unfortunate limitation given the "native" support elsewhere and needing to otherwise remember the correct value for your given platform like "sifive-p550", "spacemit-x100", etc. But, thankfully, merged overnight were these patches so GCC 17 is now correctly handling things when seeing the -mcpu=native and -mtune=native options passed on RISC-V.
[1]This patch in GCC Git from SiFive's Kito Cheng is what gets everything working. Though for RISC-V designs with multiple core types like the SpacemiT A100 and X100 combinations, GCC is picking the CPU type based upon the core where the compiler process ends up as a current limitation.
[1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=bbc5005bf48212c94501bd3918c44b38be6aa94e
GCC until now has not supported "-mcpu=native -mtune=native" on RISC-V systems if wanting to target the code generation and tuning to the CPU detected in a given system. It's an unfortunate limitation given the "native" support elsewhere and needing to otherwise remember the correct value for your given platform like "sifive-p550", "spacemit-x100", etc. But, thankfully, merged overnight were these patches so GCC 17 is now correctly handling things when seeing the -mcpu=native and -mtune=native options passed on RISC-V.
[1]This patch in GCC Git from SiFive's Kito Cheng is what gets everything working. Though for RISC-V designs with multiple core types like the SpacemiT A100 and X100 combinations, GCC is picking the CPU type based upon the core where the compiler process ends up as a current limitation.
[1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=bbc5005bf48212c94501bd3918c44b38be6aa94e