The Intel graphics compiler code in Mesa 26.3-devel has now enabled the Large GRF mode for Alchemist/DG2 and Battlemage/Xe2 graphics and VRT for Xe3 graphics.

The Large General Register File (GRF) mode on Intel graphics doubles the register space for a single hardware thread from 128 to 256 GRF registers. The Large GRF mode helps in reducing register spilling. More details on the Intel Large GRF support can be found via [1]this Intel.com documentation .

[2]This merge hitting Mesa 26.3-devel Git this weekend enables the large GRF mode for DG2 through Xe2 graphics. Large GRF was already enabled for the IGC / Intel Compute Runtime. The second commit also opens up Xe3 to use 256 GRF registers via the new [3]Variable Register Thread (VRT) functionality where as for DG2 through Xe2 is just the Large GRF feature.



[1] https://www.intel.com/content/www/us/en/docs/oneapi/optimization-guide-gpu/2023-2/small-register-mode-vs-large-register-mode.html

[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/43588

[3] https://www.phoronix.com/search/Variable%aRegister%20Thread