GCC Git Lands Fix For Missing AVX-512 Optimizations On AMD Zen 6
([AMD] 6 Hours Ago
AVX-512 Optimizations)
- Reference: 0001632002
- News link: https://www.phoronix.com/news/GCC-AMD-Zen-6-AVX-512-Opts
- Source link:
Last week marked the [1]release of GCC 16.1 as the first [2]GCC 16 stable release. While that release introduces [3]initial AMD Zen 6 "znver6" support well in advance of those next-generation AMD processors debuting, it's not yet in perfect shape with just today two missing optimizations around AVX-512 having been merged.
[4]This commit today added two missing AVX-512 optimiztions for the AMD Zen 6 path for enabling avx512_two_epilogues and avx512_masked_epilogues. The avx512_two_epilogues was a tuning parameter since GCC 15 for improving AVX-512 performance on Zen 4 / Zen 5 processors by having the compiler vectorizer produce two distinct epilogue loops for AVX-512 vectorized code. This allows handling loop leftovers more efficiently for elements that hadn't fit into a full 512-bit vector. The avx512_masked_epilogues is a tuning parameter for using two masked vector epilogues when fit for AVX-512 usage.
These AVX-512 tuning parameters are employed for both the znver4 and znver5 GCC paths but was missed out on the znver6 path until today. Unfortunately in missing out on the GCC 16.1 stable release, the hope now would be to get the patch picked up for the GCC 16.2 stable release. GCC 16.2 will be out around August if usual release traditions hold, but unfortunate for those Linux distributions in H2'2026 that will be going for GCC 16.1 rather than GCC 16.2.
As of right now in the GNU Compiler Collection Git, the Znver6 target is re-using the existing Znver5 cost table for instructions rather than having one specially crafted for the Zen 6 micro-architecture. This has been a long-time early artifact of their enablement with tuned cost tables not typically coming until later / post-launch. We'll see if they manage to get a tuned Zen 6 cost table added to the compiler in time for the end of summer GCC 16.2 release.
At least though for GCC 16.1 is this basic Zen 6 target enablement compared to the days of not seeing any open-source compiler patches until after the CPUs launch. With Zen 6 comes [5]AVX-512 BMM and other interesting ISA additions .
[1] https://www.phoronix.com/news/GCC-16.1-Released
[2] https://www.phoronix.com/search/GCC+16
[3] https://www.phoronix.com/news/AMD-Zen-6-znver6-GCC-16
[4] https://github.com/gcc-mirror/gcc/commit/da9fe0aafb08d4feeffcd2ac5782187b51a75912
[5] https://www.phoronix.com/news/AMD-Zen-6-Znver6-Binutils
[4]This commit today added two missing AVX-512 optimiztions for the AMD Zen 6 path for enabling avx512_two_epilogues and avx512_masked_epilogues. The avx512_two_epilogues was a tuning parameter since GCC 15 for improving AVX-512 performance on Zen 4 / Zen 5 processors by having the compiler vectorizer produce two distinct epilogue loops for AVX-512 vectorized code. This allows handling loop leftovers more efficiently for elements that hadn't fit into a full 512-bit vector. The avx512_masked_epilogues is a tuning parameter for using two masked vector epilogues when fit for AVX-512 usage.
These AVX-512 tuning parameters are employed for both the znver4 and znver5 GCC paths but was missed out on the znver6 path until today. Unfortunately in missing out on the GCC 16.1 stable release, the hope now would be to get the patch picked up for the GCC 16.2 stable release. GCC 16.2 will be out around August if usual release traditions hold, but unfortunate for those Linux distributions in H2'2026 that will be going for GCC 16.1 rather than GCC 16.2.
As of right now in the GNU Compiler Collection Git, the Znver6 target is re-using the existing Znver5 cost table for instructions rather than having one specially crafted for the Zen 6 micro-architecture. This has been a long-time early artifact of their enablement with tuned cost tables not typically coming until later / post-launch. We'll see if they manage to get a tuned Zen 6 cost table added to the compiler in time for the end of summer GCC 16.2 release.
At least though for GCC 16.1 is this basic Zen 6 target enablement compared to the days of not seeing any open-source compiler patches until after the CPUs launch. With Zen 6 comes [5]AVX-512 BMM and other interesting ISA additions .
[1] https://www.phoronix.com/news/GCC-16.1-Released
[2] https://www.phoronix.com/search/GCC+16
[3] https://www.phoronix.com/news/AMD-Zen-6-znver6-GCC-16
[4] https://github.com/gcc-mirror/gcc/commit/da9fe0aafb08d4feeffcd2ac5782187b51a75912
[5] https://www.phoronix.com/news/AMD-Zen-6-Znver6-Binutils