Sent out to the Linux kernel mailing list this afternoon were a set of 19 patches in preparing for some new CPU features presumably to be found with AMD's next-generation EPYC "Venice" processors.

Thanks to [1]AMD getting Zen 6 "znver6" support already into the GCC 16 compiler we already know about the new CPU ISA features coming with their next-generation processors. Now on the EPYC [2]Zen 6 "Venice" side we learn of some new features coming to benefit their next-gen servers in the enterprise.

The new features sent out are for Global Bandwidth Enforcement (GLBE), Global Slow Bandwidth Enforcement (GLSBE), and Privilege Level Zero Association (PLZA). Today's patches don't explicitly tie these new features to EPYC Venice / Zen 6 but based upon the timing and noting that the feature documentation is not yet publicly available, it points to them being so.

These bandwidth enforcement and privilege features are being tied into the Linux resource control "resctrl" code. The Linux resource control code allows managing and monitoring shared CPU resources with various other AMD EPYC features up to this point already being integrated, such as [3]BMEC and L3SBE . The patch cover letter explains GLBE, GLSBE, and PLZA as:

"Global Bandwidth Enforcement (GLBE)

AMD Global Bandwidth Enforcement (GLBE) provides a mechanism for software to specify bandwidth limits for groups of threads that span multiple QOoS Domains. This collection of QOS Domains is referred to as the GLBE Control Domain. The GLBE ceiling is a bandwidth ceiling for L3 External Bandwidth competitively shared between all threads in a COS (Class of Service) across all QOS Domains within the GLBE Control Domain. This complements L3BE L3 External Bandwidth Enforcement (L3BE) which provides L3 [External] Bandwidth control on a per QOS Domain granularity.

Global Slow Bandwidth Enforcement (GLSBE)

AMD PQoS Global Slow Bandwidth Enforcement (GLSBE) provides a mechanism for software to specify bandwidth limits for groups of threads that span multiple QOS Domains. GLSBE operates within the same GLBE Control Domains defined by GLBE. The GLSBE ceiling is a bandwidth ceiling for L3 External Bandwidth to Slow Memory competitively shared between all threads in a COS in all QOS Domains within the GLBE Control Domain. This complements L3SMBE which provides Slow Memory bandwidth control on a per QOS Domain granularity.

Privilege Level Zero Association (PLZA)

Privilege Level Zero Association (PLZA) allows the hardware to automatically associate execution in Privilege Level Zero (CPL=0) with a specific COS (Class of Service) and/or RMID (Resource Monitoring Identifier). The QoS feature set already has a mechanism to associate execution on each logical processor with an RMID or COS. PLZA allows the system to override this per-thread association for a thread that is executing with CPL=0."

The feature documentation to further explain GLBE, GLSBE, and PLZA is expected to be published in the weeks ahead. Not as exciting as other expected Zen 6 features like [4]AVX-512 BMM and [5]16 channel memory but some server administrators will surely appreciate the added functionality with GLBE / GLSBE / PLZA.

The resctrl patches for these upcoming AMD EPYC server CPU features can be found for review on the [6]Linux kernel mailing list . Good seeing more AMD Zen 6 patches emerge ahead of launch and hopefully will be upstreamed before the EPYC Venice processors debut later in the year,



[1] https://www.phoronix.com/news/AMD-Zen-6-znver6-GCC-16

[2] https://www.phoronix.com/search/Zen+6

[3] https://www.phoronix.com/news/AMD-QoS-L3SBE-BMEC

[4] https://www.phoronix.com/news/AMD-Zen-6-Znver6-Binutils

[5] https://www.phoronix.com/news/AMD-Zen-6-Venice-16c-RAM

[6] https://lore.kernel.org/lkml/aba70a013c12383d53104de0b19cfbf87690c0c3.1769029977.git.babu.moger@amd.com/