Linux 6.19 For RISC-V Brings Parallel CPU Hotplugging, Zalasr Ratified ISA Support
([RISC-V] 4 Hours Ago
Linux 6.19 RISC-V)
- Reference: 0001598092
- News link: https://www.phoronix.com/news/Linux-6.19-RISC-V
- Source link:
The RISC-V CPU architecture changes have been merged for the in-development [1]Linux 6.19 kernel.
With this new kernel RISC-V now supports CPU hot-plugging in parallel for secondary CPU cores. Secondary CPU cores can now be brought up asynchronously with the "HOTPLUG_PARALLEL" kernel feature now being supported on RISC-V for more quickly bringing up multiple CPU cores besides the primary CPU0. The CPU hot-plugging support particularly with RISC-V SoCs is primarily about dynamic enabling/disabling of CPU cores while the system is running rather than needing to handle their bring-up sequentially.
Another big feature of RISC-V with Linux 6.19 is supporting the Zalasr RISC-V ratified ISA extension. Zalasr covers RISC-V's Atomic, Load-Acquire Store-Release instructions. The code was [2]under review and the mainline kernel now supports RISC-V's ratified ISA specification for this extension.
The Zicbop extension is also now exposed to user-space with the hardware and kernel support ready. Zicbop is for the Cache Block Prefetch Operations.
The RISC-V code in the new kernel also optimizes the vector regset allocation for ptrace(), enables the user-space RAID6 test to build and run with RISC-V vectors, and various other updates. See [3]this pull for all the RISC-V highlights of Linux 6.19.
[1] https://www.phoronix.com/search/Linux+6.19
[2] https://www.phoronix.com/news/RISC-V-Linux-Zalasr-Patches
[3] https://lore.kernel.org/lkml/6b437742-e1c2-f6dd-61c8-fb3de45d3351@kernel.org/
With this new kernel RISC-V now supports CPU hot-plugging in parallel for secondary CPU cores. Secondary CPU cores can now be brought up asynchronously with the "HOTPLUG_PARALLEL" kernel feature now being supported on RISC-V for more quickly bringing up multiple CPU cores besides the primary CPU0. The CPU hot-plugging support particularly with RISC-V SoCs is primarily about dynamic enabling/disabling of CPU cores while the system is running rather than needing to handle their bring-up sequentially.
Another big feature of RISC-V with Linux 6.19 is supporting the Zalasr RISC-V ratified ISA extension. Zalasr covers RISC-V's Atomic, Load-Acquire Store-Release instructions. The code was [2]under review and the mainline kernel now supports RISC-V's ratified ISA specification for this extension.
The Zicbop extension is also now exposed to user-space with the hardware and kernel support ready. Zicbop is for the Cache Block Prefetch Operations.
The RISC-V code in the new kernel also optimizes the vector regset allocation for ptrace(), enables the user-space RAID6 test to build and run with RISC-V vectors, and various other updates. See [3]this pull for all the RISC-V highlights of Linux 6.19.
[1] https://www.phoronix.com/search/Linux+6.19
[2] https://www.phoronix.com/news/RISC-V-Linux-Zalasr-Patches
[3] https://lore.kernel.org/lkml/6b437742-e1c2-f6dd-61c8-fb3de45d3351@kernel.org/