Following [1]AMX-FP8 support , [2]AMX-AVX512 , and other new Intel CPU ISA features being added to the LLVM Clang 20 compiler codebase, the Intel [3]Diamond Rapids target is now upstreamed for allowing "-march=diamondrapids" targeting for these next-generation Xeon processors.

Similar to [4]GCC 15 adding -march=diamondrapids support last week to its codebase, the LLVM Git code for LLVM/Clang 20 now also has the Diamond Rapids target merged.

The Intel Diamond Rapids target was [5]merged yesterday into LLVM Git. (There was an initial issue leading to its revert but it since [6]re-landed .)

LLVM/Clang 20 will be out around next March with the Intel Diamond Rapids target and all of the new CPU ISA features coming with these next-gen Xeon processors. There are many new Advanced Matrix Extensions (AMX) features with Diamond Rapids along with SM3, SM4, USER MSR, and other new capabilities.



[1] https://www.phoronix.com/news/Intel-AMX-FP8-In-LLVM

[2] https://www.phoronix.com/news/AMX-AVX512-Merged-LLVM-Clang-20

[3] https://www.phoronix.com/search/Diamond+Rapids

[4] https://www.phoronix.com/news/Intel-Diamond-Rapids-March-GCC

[5] https://github.com/llvm/llvm-project/commit/826b845c9e97448395431be3e4e5da585bd98c5e

[6] https://github.com/llvm/llvm-project/commit/97836bed6357664f9b2fb87cfe10656b08309bac#diff-7435d50346a810555df89deb1f879b767ee985ace43fb3990de17fb23a47f004R671