Intel Diamond Rapids "-march=diamondrapids" Merged Into GCC 15
([Intel] 5 Hours Ago
Diamond Rapids Target)
- Reference: 0001505109
- News link: https://www.phoronix.com/news/Intel-Diamond-Rapids-March-GCC
- Source link:
The Intel [1]Diamond Rapids target has been merged in time for the upcoming [2]GCC 15 compiler release to allow for "-march=diamondrapids" targeting for leveraging the array of new CPU ISA additions found with these next-gen Xeon processors.
For a number of weeks now Intel compiler engineers have been [3]preparing GCC for the assortment of ISA additions to be ofund with this successor to Granite Rapids. The Intel engineers have [4]also been prepping the LLVM/Clang support for Diamond Rapids .
Earlier this month the patch was posted for the GNU Compiler Collection that [5]adds the Diamond Rapids target and confirms all the new ISA capabilities . It's that code that as of today is now upstream in GCC Git ahead of the GCC 15 stable release in early 2025.
With Diamond Rapids the new ISA capabilities over Granite Rapids includes AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512, AMX-FP8, AMX-TF32, AMX-TRANSPOSE, MOVRS, AMX-MOVRS, and USER_MSR. All of the AMX additions should be exciting along with finally seeing Advanced Performance Extensions (APX), AVX10.2-512, and other new notable additions. Diamond Rapids is looking very exciting from the ISA front.
"Intel Diamond Rapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB, MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16, PREFETCHI, AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512, AMX-FP8, AMX-TF32, AMX-TRANSPOSE, MOVRS, AMX-MOVRS and USER_MSR instruction set support."
[6]This GCC commit today adds the Diamond Rapids bits, [7]detection for the new Intel "Family 19" models , and allowing for "-march=diamondrapids" targeting.
The GCC 15 feature freeze is coming up soon while the GCC 15.1 stable release should be out in the usual March~April fashion, months ahead of the Diamond Rapids processors expected to appear by or around late 2025.
[1] https://www.phoronix.com/search/Diamond+Rapids
[2] https://www.phoronix.com/search/GCC+15
[3] https://www.phoronix.com/news/Intel-GCC-Diamond-Rapids-ISA
[4] https://www.phoronix.com/news/AMX-AVX512-Merged-LLVM-Clang-20
[5] https://www.phoronix.com/news/Intel-Diamond-Rapids-APX-AVX10
[6] https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=74ae651bd61a7128c77ca08328956564fd49a23b
[7] https://www.phoronix.com/news/Intel-Diamond-Rapids-Family-19
For a number of weeks now Intel compiler engineers have been [3]preparing GCC for the assortment of ISA additions to be ofund with this successor to Granite Rapids. The Intel engineers have [4]also been prepping the LLVM/Clang support for Diamond Rapids .
Earlier this month the patch was posted for the GNU Compiler Collection that [5]adds the Diamond Rapids target and confirms all the new ISA capabilities . It's that code that as of today is now upstream in GCC Git ahead of the GCC 15 stable release in early 2025.
With Diamond Rapids the new ISA capabilities over Granite Rapids includes AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512, AMX-FP8, AMX-TF32, AMX-TRANSPOSE, MOVRS, AMX-MOVRS, and USER_MSR. All of the AMX additions should be exciting along with finally seeing Advanced Performance Extensions (APX), AVX10.2-512, and other new notable additions. Diamond Rapids is looking very exciting from the ISA front.
"Intel Diamond Rapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB, MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16, PREFETCHI, AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512, AMX-FP8, AMX-TF32, AMX-TRANSPOSE, MOVRS, AMX-MOVRS and USER_MSR instruction set support."
[6]This GCC commit today adds the Diamond Rapids bits, [7]detection for the new Intel "Family 19" models , and allowing for "-march=diamondrapids" targeting.
The GCC 15 feature freeze is coming up soon while the GCC 15.1 stable release should be out in the usual March~April fashion, months ahead of the Diamond Rapids processors expected to appear by or around late 2025.
[1] https://www.phoronix.com/search/Diamond+Rapids
[2] https://www.phoronix.com/search/GCC+15
[3] https://www.phoronix.com/news/Intel-GCC-Diamond-Rapids-ISA
[4] https://www.phoronix.com/news/AMX-AVX512-Merged-LLVM-Clang-20
[5] https://www.phoronix.com/news/Intel-Diamond-Rapids-APX-AVX10
[6] https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=74ae651bd61a7128c77ca08328956564fd49a23b
[7] https://www.phoronix.com/news/Intel-Diamond-Rapids-Family-19
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