Going back to earlier in the year AMD Linux engineers have been prepping the kernel for [1]PCI Express TLP Processing Hints (TPH) support that allows for hints that can be injected to improve latency and lowering traffic congestion when there are several possible cache locations on the server with the TPH noting the optimal location of a Transaction Layer Packet (TLP). This PCIe TPH support is set to be merged upstream with the forthcoming Linux 6.13 cycle.

PCIe TPH support is an exciting addition to the PCI Express specification. AMD engineers have been pursuing the Linux support for it with this capability being found in the new 5th Gen AMD EPYC "Turin" platform. AMD engineers spent hte past several months working out the core Linux infrastructure for PCIe TPH as well as adapting toe Broadcom BNXT network driver to demonstrate PCIe TPH usage.

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This PCIe TPH support goes along with [3]AMD Smart Data Cache Injection as part of the new I/O functionality with the 5th Gen AMD EPYC server processors. SDCI in turn allows direct insertion of data from I/O devices into the L3 cache.

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Queued up this past week into [5]pci.git's "next" Git branch is the "TPH" branch that contains AMD's PCIe TPH enablement work. Thus for the Linux 6.13 merge window kicking off during the back half of November, this TPH functionality should be merged. Linux 6.13 in turn should be out as stable in February. It's too bad AMD wasn't able to get this functionality all upstreamed into the kernel ahead of the EPYC 9005 series debut earlier this month, but in any event it's on the way.

"TPH (TLP Processing Hints) is a PCIe feature that allows endpoint devices to provide optimization hints for requests that target memory space. These hints, in a format called Steering Tags (STs), are embedded in the requester's TLP headers, enabling the system hardware, such as the Root Complex, to better manage platform resources for these requests.

For example, on platforms with TPH-based direct data cache injection support, an endpoint device can include appropriate STs in its DMA traffic to specify which cache the data should be written to. This allows the CPU core to have a higher probability of getting data from cache, potentially improving performance and reducing latency in data processing."

For those interested in PCIe TLP Processing Hints functionality for the Linux kernel can see [6]this documentation commit that goes over all the technical details of the support.

The [7]EPYC 9005 Linux support overall is in great shape besides a few extra new features like PCIe TPH taking longer time to bake and make it upstream. The AMD EPYC 9005 series Linux performance is downright incredible as I've shown in a number of benchmarks already and more follow-up tests are on the way.



[1] https://www.phoronix.com/news/AMD-PCIe-TPH-Linux-Patches

[2] https://www.phoronix.com/image-viewer.php?id=2024&image=amd_turin_pcie_lrg

[3] https://www.phoronix.com/news/AMD-EPYC-SDCI-Cache-Injection

[4] https://www.phoronix.com/image-viewer.php?id=2024&image=amd_epyc_tph_lrg

[5] https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=next

[6] https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=next&id=48d0fd2b903e397c2a9621ab35f3d8877f61aee4

[7] https://www.phoronix.com/search/EPYC+9005