Going back to 2016 we've known of [1]NVIDIA beginning to use RISC-V to replace their Falcon micro-controller and other micro-controllers within their graphics processors to using this common open-source ISA. That use has continued to grow and an unofficial estimate now puts it at around one billion RISC-V cores shipping in 2024 NVIDIA chips.

Frans Sijstermans of NVIDIA was a keynote presenter at the RISC-V Summit this week in Santa Clara, California. His keynote was titled "RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billions of Processors." The recording and slides have yet to be posted but Nick Brown, a Senior Research Fellow with the University of Edinburgh had shared on [2]Twitter/X some pictures from the presentation.

The "billions" in the title appear to be accurate. Frans estimates that there are around one billion RISC-V cores shipping within the 2024 NVIDIA chips alone to grasp the scale at which they are relying on RISC-V for various MCUs and controllers within their chips. With now having phased out their former Falcon micro-controller in favor of all RISC-V, there are between 30~40 unique RISC-V IP within each modern NVIDIA chip.

RISC-V within NVIDIA hardware is responsible for various data processing, power management and other chip/system level tasks like security, camera and display handling, and other tasks. The [3]GPU System Processor (GSP) commonly talked about on Phoronix for its driver interactions and doing more heavy lifting from the driver these days is one prime RISC-V example within recent generations of NVIDIA GPUs.

Fascinating to see the scale of RISC-V use within NVIDIA.



[1] https://www.phoronix.com/news/NVIDIA-RISC-V-Next-Gen-Falcon

[2] https://x.com/NickBrownHPC/status/1848868750684262567

[3] https://www.phoronix.com/search/GPU+System+Processor