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Last week I had the pleasure to be out in Los Angeles for the AMD Tech Day focused on their new Ryzen 9000 "Granite Ridge" and Ryzen AI 300 "Strix Point" processors. This was an exciting event with many new details shared around [2]Zen 5 CPU cores and the RDNA 3.5 integrated graphics found with the upcoming Ryzen AI 300 series mobile processors. The embargo concerning those architectural details have now expired while the review/benchmarking embargo isn't until a later date.

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The Zen 5 Tech Day went into detail over the architectural improvements to be found with the Ryzen AI 300 and Ryzen 9000 series processors. In the months ahead will also be the next-generation EPYC server processors built atop Zen 5.

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One of the interesting changes with Zen 5 is having a full 512-bit data path for AVX-512. Zen 4 introduced AVX-512 on the AMD side using a "double pumped" implementation using a 256-bit data path. [6]Zen 4's AVX-512 proved to be remarkably efficient and very performant . Now with Zen 5 is a full 512-bit data path. Though for some Zen 5 SKUs the "double pumped" AVX-512 implementation will be retained. Like for smaller/mobile Ryzen SKUs may stick to a double pumped AVX-512 while the desktop and higher-end parts will have a full 512-bit data path. Can't wait to benchmark the improved AVX-512 support on Zen 5!

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[1] https://www.phoronix.com/image-viewer.php?id=amd-zen5-ryzen-9000&image=amd_zen5_1_lrg

[2] https://www.phoronix.com/search/Zen+5

[3] https://www.phoronix.com/image-viewer.php?id=amd-zen5-ryzen-9000&image=amd_zen5_2_lrg

[4] https://www.phoronix.com/image-viewer.php?id=amd-zen5-ryzen-9000&image=amd_zen5_3_lrg

[5] https://www.phoronix.com/image-viewer.php?id=amd-zen5-ryzen-9000&image=amd_zen5_4_lrg

[6] https://www.phoronix.com/review/amd-zen4-avx512

[7] https://www.phoronix.com/image-viewer.php?id=amd-zen5-ryzen-9000&image=amd_zen5_6_lrg