Back in May there were Linux kernel patches posted as a workaround for Arm CPU errata around the [1]Speculative Store Bypass (SSB) handling. Initially this workaround was just noted as the Cortex-X4 and Neoverse-V3 as being affected, but now it turns out many more exciting Arm processor cores are impacted.

Spectre V4 / Speculative Store Bypass has been around for years and newer Arm CPUs mitigated, but the more recent issue at hand is Arm CPU errata with the mitigation. With affected processors, MSR write to the SSBS (Speculative Store Bypass Safe) special purpose register does not affect subsequent speculative instructions. In turn this issue can lead to speculative store bypassing for a period of time. The Linux workaround to this newer errata is to have a speculation barrier after MSR writes to the SSBS register.

Besides the Cortex X4 and Neoverse V3, Arm engineers have now extended this SSBS workaround to other affected cores including the A710, A720, X2, X3, X925, N2, and V2.

[2]This patch has been added to the ARM64 kernel's "for-next/errata" Git branch ahead of the Linux 6.11 merge window. Thus with Linux 6.11 the code will land for expanding this speculative SSBS workaround to the additional affected models.



[1] https://www.phoronix.com/search/Speculative+Store+Bypass

[2] https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/commit/?h=for-next/errata&id=75b3c43eab594bfbd8184ec8ee1a6b820950819a