The World's Tallest Chip Defies the Limits of Computing: Goodbye To Moore's Law? (elpais.com)
- Reference: 0179966466
- News link: https://hardware.slashdot.org/story/25/11/04/235241/the-worlds-tallest-chip-defies-the-limits-of-computing-goodbye-to-moores-law
- Source link: https://english.elpais.com/technology/2025-11-04/the-worlds-tallest-chip-defies-the-limits-of-computing-goodbye-to-moores-law.html
> For decades, the progress of electronics has followed a simple rule: smaller is better. Since the 1960s, each new generation of chips has packed more transistors into less space, fulfilling the famous Moore's Law. Formulated by Intel co-founder Gordon Moore in 1965, this law predicted that the number of transistors in an integrated circuit approximately doubles each year. But this race to the minuscule is reaching its physical limits. Now, an international team of scientists is proposing a solution as obvious as it is revolutionary: if we can't keep reducing the size of chips, let's build them up.
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> Xiaohang Li, a researcher at King Abdullah University of Science and Technology (KAUST) in Saudi Arabia, and his team have [2]designed a chip with 41 vertical layers of semiconductors and insulating materials , approximately ten times higher than any previously manufactured chip. The work, recently [3]published in the journal Nature Electronics , not only represents a technical milestone but also opens the door to a new generation of flexible, efficient, and sustainable electronic devices. "Having six or more layers of transistors stacked vertically allows us to increase circuit density without making the devices smaller laterally," Li explains. "With six layers, we can integrate 600% more logic functions in the same area than with a single layer, achieving higher performance and lower power consumption."
[1] https://slashdot.org/~dbialac
[2] https://english.elpais.com/technology/2025-11-04/the-worlds-tallest-chip-defies-the-limits-of-computing-goodbye-to-moores-law.html
[3] https://www.nature.com/articles/s41928-025-01469-0
Cool (Score:3)
Iâ(TM)d always assumed thermals and cost would be the limiting factor in chip thickness.
Re:Cool (Score:4, Insightful)
This was my thought too - if you have essentially 6 layers of silicon with insulators between to create 600% of the transistor density, you're also consuming >600% of the power (nothing is ever 100% efficient) and therefore producing >600% of the wattage to dissipate without a corresponding size in radiative surface area.
How do you not cook the center of the cube when we're already throwing 70W into a single chip the size of your fingernail? Maybe central heat pipes that each layer hooks up to, running vertically through the die? And how much area per layer do you lose to that, at what increased manufacturing complexity (read: cost and reduction in yields)?
I'm sure those are all answerable engineering questions to present if the value is there. And my guess is that since it's very obvious that stacking chips is a sure-fire way to increase transistor area, that the value hasn't been worth the added complexity to solve the inherent problems because die shrinks were always cheaper and easier to do... right up until they aren't.
It's good that someone is asking the question and showing that it can be done. But I'd wager [paywall so couldn't RTFA to confirm] that they aren't exactly stacking up the highest performance Xeon or Epyc chips 41 high and running them at full throttle.
Re: (Score:2)
It actually is interconnect first, thermals second and then things like clock distribution and power. There always was more space for logic, but that logic could then not be used.
I don't get it (Score:2)
Where's the "defies the limits of computing" part?
Re: (Score:2)
I assume they mean a 10x jump is outpacing Moore's law.
I would bet though that it'll take long enough to commercialize that it will fall right in place with Moore's law.
Re: (Score:3)
> Where's the "defies the limits of computing" part?
Defies the thermal limits, probably.
Re: (Score:2)
Moore's Law assumes two dimensional architecture, I don't think that three dimensional layouts were even considered to be possible at the time much less something someone would want to do.
Re: (Score:2)
Nowhere. This is a meaningless stunt.
Heat dissipation? Yields? (Score:3)
How do you get the heat out of a bunch of CPU cores that are sandwiched between layers of additional heat-generating cores?
I wonder how much effort it would take to get the defect rate low enough to be commercially viable. It's a hard problem today. Does this make it easier because you can use wider features and just build upward to get the desired number of features? Or does everything just get a lot harder to do consistently?
Re: (Score:1)
I wonder if the peltier effect / Peltier Cooling would be the solution to this, obviously in a very thin form. You could use the outside edges of the chip substrate to move the heat too, however coolers would require re-design, but that's a possible way to limit the heat between the layers by adding Peltier type cooling in the sandwich.
Re: Heat dissipation? Yields? (Score:2)
Turns out, they're targeting low power applications, so heat isn't the same challenge that it is with desktop and server CPUs.
But since they're not trying to push the envelope of Moore's law, I wonder why stacking is needed in the first place.
Re: (Score:3)
My guess is that they aren't targeting performance, but rather making a lower power system-on-chip that really is a fully-featured system-on-a-chip and incorporates lots of low-power and low-heat peripheral crap like I2C / serial / USB / SATA in addition to RAM, flash storage, NIC, etc. - put the highest wattage bits on the top for direct interface with the heat spreader, and stack the other stuff below with some thermal magic in the sandwich to move as much heat from the lower layers to the edges as possib
Re: (Score:2)
> How do you get the heat out of a bunch of CPU cores that are sandwiched between layers of additional heat-generating cores?
Easy, you just use synthetic diamond for the substrate. /s
Cooling? (Score:2)
One of the things about making something with a larger volume is that you will also decrease the amount of heat it can get rid of.
How are they going to cool these new 3D chips?
Re: (Score:1)
I suspect they'll eventually end up being designed akin to tall buildings with corridors between adjacent buildings ever few floors. The coolant will run in between.
Re: (Score:2)
I think it would have to be liquid cooling
the number of layers wasn't the issue, the thermal (Score:2)
From my understanding, the number of layers wasn't the issue ever, the thermal issues were. When you stack, you start compound the heat issues. With the tech these guys are talking about, the performance starts to degrade at 50c. Any real world scenario using these chips will require highly specialized cooling solutions.
So while great, they managed to stack vertically higher than others before... is the size/density benefit offset by the cooling requirements? Or is this one of those theoretical wins tha
Say hello to Wirth's law (Score:2)
It's sadly still relevant.
Re: (Score:2)
OTOH the nice thing about software is that it's easy to update, so anyone is free to replace their slow/inefficient software with a faster/efficient version as soon as they obtain it, at which point their fast hardware should run the efficient software very quickly. Nothing (except possibly bad management decisions?) is preventing anyone from creating efficient software, either.
Re: (Score:2)
The industry has forgotten how to write efficient software. We've had multiple generations brought up believing that memory is free and that increasingly fast computers will magically solve any performance problems.
For reasons I can't even begin to comprehend, people still believe that nonsense.
Ages ago, we'd caution developers against 'premature optimization' as a hedge against needless complexity. These days, the trade-off is the same, just flipped on its head: The code that's easy to read and maintain
Every Two Years (Score:5, Informative)
Moore tells us that density doubles every two years, not every year. Also, Samsung has been producing 96-layer V-NAND dies at scale since 2019.
Re: (Score:2)
This is what I was thinking - RAM guys have been stacking chips for a hell of a long time. First as actual package stacks on the DIMM - I remember seeing some very dense modules in the DDR2 days with stacked packages; and then as you correctly point out: Samsung has been layering dies inside the package for years as a microscopic version of stacking chip packages.
It's also why DIMMs have heat spreaders on them now.
Re: (Score:2)
Stacking chips is not the same as a monolithic chip with multiple active layers. When chips are stacked, each chip can be tested before stacking, and the final yield becomes a question of successful interconnect and not damaging chips during assembly. With multilayer chups each layer must be perfect for the device to work.
I'd guess that they're not using a process with the smallest geometry. That way they can have a process that is basically very high yield for each layer; the resulting die will have accep
Re: (Score:2)
What Samsung does is stack dies on top of each other. What these people here do is a die with more layers. But this is very likely just a stunt that is non-viable for any real use.
Re: (Score:2)
It's not a law of nature. It's also quite a stretch from what he actually said. [1]This is where it comes from [intel.com]
[1] https://newsroom.intel.com/wp-content/uploads/sites/11/2018/05/moores-law-electronics.pdf
Soon they'll be talking about (Score:1)
"Intel bricks inside!"
How tall ... (Score:2)
... can it get before all the engineers start speaking different languages?
4 layers? (Score:2)
We've never had more than 4 layers of silicon? That's surprising to me.
Re: (Score:3)
It is _really_ difficult to do more layers. If you have simple interconnect (FLASH or cache chips), you can stack chips, but more layers on a single chip comes with a ton of problems.
This thing here is probably just a stunt and will not be ready for production, ever.