Qualcomm takes RISC on Arm alternative with Ventana acquisition
(2025/12/10)
- Reference: 1765398317
- News link: https://www.theregister.co.uk/2025/12/10/qualcomm_riscv_arm_ventana/
- Source link:
Qualcomm could soon be serving up RISC-V cores alongside its custom Arm ones following the acquisition of Ventana Micro Systems on Wednesday.
Founded in 2018, Ventana has [1]developed several generations of high-performance RISC-V-based CPU designs aimed at datacenter and enterprise applications.
The terms of the acquisition weren't disclosed, but Qualcomm intends to continue the development of Ventana's designs in parallel with the custom Arm-based Oryon cores used in its Snapdragon X-series of chips.
[2]
"We believe the RISC-V instruction set architecture has the potential to advance the frontier on CPU technology, enabling innovation across products," Durga Malladi, executive VP of technology planning, edge solutions and datacenter at Qualcomm, said in a canned [3]statement . "The acquisition of Ventana Micro Systems marks a pivotal step in our journey to deliver industry-leading RISC-V based CPU technology across products."
[4]
[5]
Qualcomm is no stranger to RISC-V. The company has been toying with the instruction set architecture (ISA) for years now. The chipset giant has been using RISC-V microcontrollers in its SoCs going back to the [6]Snapdragon 865 launched in 2019. In 2023, the company launched a [7]collaboration with Google to bring low-power, high-performance RISC-V-based chips to wearables.
However, the acquisition of Ventana points to the possibility of a far more potent class of RISC-V processors from Qualcomm. Ventana's Veyron V2 [8]chiplet design features up to 32 RISC-V RVA23-compatible CPU cores clocked at up to 3.85 GHz, and is equipped with up to 1.5 MB of L2 cache per core and 128 MB of shared L3 cache.
[9]
Each core is equipped with both a 512-bit vector unit based on the RVV 1.0 spec, and a custom matrix math accelerator for AI and machine learning applications. According to Ventana, the matrix unit is good for 0.5 TOPS (INT8) per GHz per core.
For higher performance applications, Ventana's design allows multiple chiplets to be assembled into a system-in-package. We previously [10]reported Ventana's V2 chiplets were originally expected to enter production in the second half of 2024. However, the company's website now shows silicon is expected in early 2026.
Ventana has also teased its next-gen Veyron V3 chiplet designs, which will promise higher clock speeds up to 4.2 GHz and an enhanced matrix math unit with support for the FP8 data type.
[11]Tenstorrent QuietBox tested: A high-performance RISC-V AI workstation trapped in a software blackhole
[12]HPC won't be an x86 monoculture forever – and it's starting to show
[13]Bolt Graphics unveils Zeus GPU built on RISC-V and path tracing tech
[14]Chip designer SiFive aims to cram more RISC-V cores into AI chips
Qualcomm hasn't said if and when we can expect to see its chips based on Ventana's RISC-V IP. In May, the company announced it was [15]returning to the datacenter CPU space after a failed attempt to make Arm-based servers in 2018.
These products are broadly expected to be based on core technologies obtained when Qualcomm bought Arm-based CPU vendor Nuvia, which had initially targeted server applications prior to the acquisition in 2021.
[16]
That acquisition, we'll note, wasn't without controversy. In 2022, Arm sued Qualcomm over an [17]alleged breach of its licenses tied to Nuvia. Late last year, a jury sided with Qualcomm in the case, and in October, a judge quashed Arm's appeal.
However, Qualcomm's legal battle with Arm isn't over. A countersuit brought by the California chip biz is still [18]ongoing . But, at least now, Qualcomm has a potential alternative should its relationship with Arm deteriorate further. ®
Get our [19]Tech Resources
[1] https://www.theregister.com/2023/11/07/ventana_riscv_server/
[2] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[3] https://www.qualcomm.com/news/releases/2025/12/qualcomm-acquires-ventana-micro-systems--deepening-risc-v-cpu-ex
[4] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[5] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[6] https://www.theregister.com/2019/12/03/qualcomm_snapdragon_tech_summit/
[7] https://www.theregister.com/2023/10/18/qoogle_qualcomm_riscv_snapdragon/
[8] https://www.ventanamicro.com/technology/risc-v-cpu-ip/
[9] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[10] https://www.theregister.com/2023/11/07/ventana_riscv_server/
[11] https://www.theregister.com/2025/11/27/tenstorrent_quietbox_review/
[12] https://www.theregister.com/2025/11/27/arm_riscv_hpc/
[13] https://www.theregister.com/2025/10/29/bolt_graphics_zeus_gpu/
[14] https://www.theregister.com/2025/09/08/sifive_ai_cpu_cores/
[15] https://www.theregister.com/2025/05/19/qualcomm_datacenter_products/
[16] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[17] https://www.theregister.com/2024/12/23/qualcomm_arm_trial/
[18] https://www.theregister.com/2025/10/01/arms_last_legal_claim_against/
[19] https://whitepapers.theregister.com/
Founded in 2018, Ventana has [1]developed several generations of high-performance RISC-V-based CPU designs aimed at datacenter and enterprise applications.
The terms of the acquisition weren't disclosed, but Qualcomm intends to continue the development of Ventana's designs in parallel with the custom Arm-based Oryon cores used in its Snapdragon X-series of chips.
[2]
"We believe the RISC-V instruction set architecture has the potential to advance the frontier on CPU technology, enabling innovation across products," Durga Malladi, executive VP of technology planning, edge solutions and datacenter at Qualcomm, said in a canned [3]statement . "The acquisition of Ventana Micro Systems marks a pivotal step in our journey to deliver industry-leading RISC-V based CPU technology across products."
[4]
[5]
Qualcomm is no stranger to RISC-V. The company has been toying with the instruction set architecture (ISA) for years now. The chipset giant has been using RISC-V microcontrollers in its SoCs going back to the [6]Snapdragon 865 launched in 2019. In 2023, the company launched a [7]collaboration with Google to bring low-power, high-performance RISC-V-based chips to wearables.
However, the acquisition of Ventana points to the possibility of a far more potent class of RISC-V processors from Qualcomm. Ventana's Veyron V2 [8]chiplet design features up to 32 RISC-V RVA23-compatible CPU cores clocked at up to 3.85 GHz, and is equipped with up to 1.5 MB of L2 cache per core and 128 MB of shared L3 cache.
[9]
Each core is equipped with both a 512-bit vector unit based on the RVV 1.0 spec, and a custom matrix math accelerator for AI and machine learning applications. According to Ventana, the matrix unit is good for 0.5 TOPS (INT8) per GHz per core.
For higher performance applications, Ventana's design allows multiple chiplets to be assembled into a system-in-package. We previously [10]reported Ventana's V2 chiplets were originally expected to enter production in the second half of 2024. However, the company's website now shows silicon is expected in early 2026.
Ventana has also teased its next-gen Veyron V3 chiplet designs, which will promise higher clock speeds up to 4.2 GHz and an enhanced matrix math unit with support for the FP8 data type.
[11]Tenstorrent QuietBox tested: A high-performance RISC-V AI workstation trapped in a software blackhole
[12]HPC won't be an x86 monoculture forever – and it's starting to show
[13]Bolt Graphics unveils Zeus GPU built on RISC-V and path tracing tech
[14]Chip designer SiFive aims to cram more RISC-V cores into AI chips
Qualcomm hasn't said if and when we can expect to see its chips based on Ventana's RISC-V IP. In May, the company announced it was [15]returning to the datacenter CPU space after a failed attempt to make Arm-based servers in 2018.
These products are broadly expected to be based on core technologies obtained when Qualcomm bought Arm-based CPU vendor Nuvia, which had initially targeted server applications prior to the acquisition in 2021.
[16]
That acquisition, we'll note, wasn't without controversy. In 2022, Arm sued Qualcomm over an [17]alleged breach of its licenses tied to Nuvia. Late last year, a jury sided with Qualcomm in the case, and in October, a judge quashed Arm's appeal.
However, Qualcomm's legal battle with Arm isn't over. A countersuit brought by the California chip biz is still [18]ongoing . But, at least now, Qualcomm has a potential alternative should its relationship with Arm deteriorate further. ®
Get our [19]Tech Resources
[1] https://www.theregister.com/2023/11/07/ventana_riscv_server/
[2] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[3] https://www.qualcomm.com/news/releases/2025/12/qualcomm-acquires-ventana-micro-systems--deepening-risc-v-cpu-ex
[4] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[5] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[6] https://www.theregister.com/2019/12/03/qualcomm_snapdragon_tech_summit/
[7] https://www.theregister.com/2023/10/18/qoogle_qualcomm_riscv_snapdragon/
[8] https://www.ventanamicro.com/technology/risc-v-cpu-ip/
[9] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[10] https://www.theregister.com/2023/11/07/ventana_riscv_server/
[11] https://www.theregister.com/2025/11/27/tenstorrent_quietbox_review/
[12] https://www.theregister.com/2025/11/27/arm_riscv_hpc/
[13] https://www.theregister.com/2025/10/29/bolt_graphics_zeus_gpu/
[14] https://www.theregister.com/2025/09/08/sifive_ai_cpu_cores/
[15] https://www.theregister.com/2025/05/19/qualcomm_datacenter_products/
[16] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_specialfeatures/futureofthedatacenter&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33aTn7k1NhMxPmj56lBUIM3AAAAQg&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[17] https://www.theregister.com/2024/12/23/qualcomm_arm_trial/
[18] https://www.theregister.com/2025/10/01/arms_last_legal_claim_against/
[19] https://whitepapers.theregister.com/