Penn State boffins create silicon-free two-dimensional computer
- Reference: 1750101615
- News link: https://www.theregister.co.uk/2025/06/16/penn_state_boffins_2d_cmos/
- Source link:
The team, led by Pennsylvania State University engineering science professor Saptarshi Das, published a [1]paper last week detailing the design and construction of their 2D one instruction set computer (OISC) based on the same complementary metal-oxide-semiconductor ( [2]CMOS ) design that's a standard part of modern silicon-based computers. OISC is a minimalist abstract machine model that performs all operations using a single, universal instruction.
Does that mean we can expect to live through a post-silicon, 2D computing revolution? It won't be quite like that, Das told us. Rather, 2D CMOS computers will have specialized uses.
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"They could become competitive in specialized domains such as edge AI, neuromorphic systems, or flexible electronics," Das told us.
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The 2D machine they built is silicon-free, using molybdenum disulfide for n-type and tungsten diselenide for p-type transistors. The material pair "offer complementary electrical characteristics, relatively high mobility, and have demonstrated scalable growth via metal–organic chemical vapor deposition (MOCVD)," Das told The Register in an email. MOCVD was used to fabricate the team's 2D CMOS platform on sapphire wafers, with transistor channels just one atom thick.
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An electron microscope image of the 2D CMOS circuit showing p-type and n-type transistors in orange and blue, respectively - Click to enlarge
CMOS systems need both n- and p-type transistors (which move electrons along a circuit by having an excess and deficiency of electrons, respectively) to achieve the goal of CMOS computing - energy efficiency and reusability. That's why the team's 2D CMOS design is such a breakthrough, according to Das.
We have demonstrated, for the first time, a CMOS computer built entirely from 2D materials
"We have demonstrated, for the first time, a CMOS computer built entirely from 2D materials," [7]Das said in an announcement on the Penn State website.
That's not to say Das' system is fast, mind you. According to the research paper, the Penn State team only managed to achieve an operating frequency of up to 25 kHz at supply voltages below 3 V. This speed was limited primarily by parasitic capacitance - unwanted capacitance between closely spaced circuit elements that impairs switching performance.
While parasitic capacitance is a problem now, Das told us his team is working on solving that issue now. According to the team's simulations, if the parasitic capacitance issue is resolved, "2D-CMOS logic gates could achieve delays as low as 200 [picoseconds], equivalent to operating frequencies of ~5 GHz."
Is a 2D computing future coming soon?
With a proof-of-concept built and tested, the next obvious question is whether such a system could be scaled up. Das thinks so.
"[Scalability] is one of the most critical aspects of our work," Das told us. "While some steps (e.g., layer alignment and transfer) are still manual, most of the process is compatible with industry tools and can be automated."
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The team fabricated more than 2,000 transistors on a 2-inch sapphire wafer, achieving a 95 percent functional yield, Das told us. He expects the project to be able to scale up without much issue, provided they can automate the rest of those processes.
[9]Please sir, may we have some Moore? Doesn't look that way
[10]A closer look at Intel and AMD's different approaches to gluing together CPUs
[11]Things are going to get weird as the nanometer era draws to a close
[12]Nvidia GPU roadmap confirms it: Moore's Law is dead and buried
The test chip was also stable, Das said, with the circuit showing "robust functionality under ambient conditions over the course of repeated measurements." Long-term reliability studies, which will include bias stress, temperature cycling and radiation tolerance, are part of the next phase of development, he told us.
Along with that testing and work to reduce parasitic capacitance, Das said his team is now working to expand instruction sets and memory complexity to enable the creation of more powerful processors, scaling down gate lengths to increase performance and integrating new gate dielectrics. Work to make this practical is ongoing, in other words. ®
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[1] https://www.nature.com/articles/s41586-025-08963-7
[2] https://www.sciencedirect.com/topics/earth-and-planetary-sciences/cmos
[3] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_offbeat/science&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=2&c=2aFCT9rP5ui9jtSu596LsjgAAAQs&t=ct%3Dns%26unitnum%3D2%26raptor%3Dcondor%26pos%3Dtop%26test%3D0
[4] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_offbeat/science&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44aFCT9rP5ui9jtSu596LsjgAAAQs&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[5] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_offbeat/science&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=3&c=33aFCT9rP5ui9jtSu596LsjgAAAQs&t=ct%3Dns%26unitnum%3D3%26raptor%3Deagle%26pos%3Dmid%26test%3D0
[6] https://regmedia.co.uk/2025/06/16/electron-microscope-2d-cmos.jpg
[7] https://www.psu.edu/news/research/story/worlds-first-2d-non-silicon-computer-developed
[8] https://pubads.g.doubleclick.net/gampad/jump?co=1&iu=/6978/reg_offbeat/science&sz=300x50%7C300x100%7C300x250%7C300x251%7C300x252%7C300x600%7C300x601&tile=4&c=44aFCT9rP5ui9jtSu596LsjgAAAQs&t=ct%3Dns%26unitnum%3D4%26raptor%3Dfalcon%26pos%3Dmid%26test%3D0
[9] https://www.theregister.com/2025/04/07/opinion_column_moores_law/
[10] https://www.theregister.com/2024/10/24/intel_amd_packaging/
[11] https://www.theregister.com/2024/01/29/nanometer_era_angstrom/
[12] https://www.theregister.com/2025/03/29/nvidia_moores_law/
[13] https://whitepapers.theregister.com/
> Clock speed of 25 kHz means 2D CMOS system won't run Doom quite yet
Yeah, but can't it run Crysis?
Gaze into the temporal distance and you might spot the end of the age of silicon looming somewhere out there
Into the distance? We're in the era of Megawatt racks.
Timecheck
So, firstly this is not 2D. The tracks pass over each other, so the equivalent macroscopic topology is a double-sided circuit board of the kind which was ubiquitous in the 1980s. The first CPUs used only single-sided boards, genuinely 2D and not mere marketing-speak 2D, with the first microprocessors being similarly restricted on-chip.
Group III-V (silicon-free) semiconductors were used to create high-speed devices for specialist applications.
So here we are, back to 1970/80s technology. I am not entirely clear how a selenium compound is more commercially viable than, say, gallium-aluminium-arsenide. But then, I seem to have lost my coloured pencils.
P.S. But if it can run Moon Lander, I'm in!
An operating frequency of 25 kHz
The current speed is rather immaterial. A totally new design with new materials will not be as fast or efficient as the fully optimized tool chain that produces silicon chips.
There seem to be ample room for improvement and optimization. And one atom thick channels sound already like a major achievement.
The one instruction that is the instruction set of this computer turns out to be [1]reverse subtract and skip if borrow (RSSB) .
Not something I would be eager to program in. It makes assembler look positively user friendly high level abstract. But you can always build a C compiler for it. But I think it must be easy to find more CMOS efficient instruction sets.
[1] https://esolangs.org/wiki/RSSB
200ps switching time is NOT equivalent to 5 GHz
Processors that are clocked at 5 GHz switch a number of gates during that cycle, not just one. The "3nm" class transistors in the latest CPUs switch at well over 100 GHz.