LLVM Merges Support The For Tenstorrent TT-Ascalon-D8 RISC-V CPU
([LLVM] 28 November 06:42 AM EST
TT-Ascalon-D8)
Adding to the interesting code building up for next spring's release of the LLVM 20 compiler stack is having the Tenstorrent TT-Ascalon D8 as the newest RISC-V processor target.