It Turns Out Intel TDX Doesn't Need So Much Cache Flushing
([Intel] 2 Hours Ago
Intel TDX Cache Flushing)
- Reference: 0001664517
- News link: https://www.phoronix.com/news/Intel-TDX-Less-Cache-Flushing
- Source link:
Intel Trust Domain Extensions (TDX) for confidential computing with VMs has assumed the need to perform cache flushing when transitioning memory between KeyIDs used by the total memory encryption (MKTME) for unique AES encryption keys. But it's turned out to be unneeded and the Linux kernel is working now to reduce the excessive cache flushing.
In what may help Intel TDX VM performance by eliminating unnecessary flushing of the caches, the Linux kernel has a set of patches pending to eliminate the software-driven cache flushes as its being properly handled by the Intel Xeon processor hardware.
Intel software engineer Rick Edgecombe explained of the patch series " [1]Drop unneeded cache flushing " on the Linux kernel mailing list:
"In the early days of TDX it was assumed the HW would need some cache flushing help around transitioning memory between KeyIDs, and so TDX arch was designed to specify how the VMM needed to help the module perform this. But it turned out the HW was able to handle these issues without SW help. For some reason the TDX arch around performing the flushes remained. Now the TDX arch is getting fixed and Linux can remove the code that was helping perform this unneeded cache flushing. The changes will appear in
a future documentation update."
Apparently all finalized TDX hardware don't require the extra software-driven cache flushing around the KeyIDs but the Intel documentation was never updated to reflect that, but those Intel docs will be updated in the next revision. Intel TDX initially appeared in select Xeon Sapphire Rapids processors but has been supported by all Xeon processors since Emerald Rapids.
This leads to simpler kernel code but no word in the patch messages of any expected performance impact.
[1] https://lore.kernel.org/lkml/20261015191710.3632302-1-rick.p.edgecombe@intel.com/
In what may help Intel TDX VM performance by eliminating unnecessary flushing of the caches, the Linux kernel has a set of patches pending to eliminate the software-driven cache flushes as its being properly handled by the Intel Xeon processor hardware.
Intel software engineer Rick Edgecombe explained of the patch series " [1]Drop unneeded cache flushing " on the Linux kernel mailing list:
"In the early days of TDX it was assumed the HW would need some cache flushing help around transitioning memory between KeyIDs, and so TDX arch was designed to specify how the VMM needed to help the module perform this. But it turned out the HW was able to handle these issues without SW help. For some reason the TDX arch around performing the flushes remained. Now the TDX arch is getting fixed and Linux can remove the code that was helping perform this unneeded cache flushing. The changes will appear in
a future documentation update."
Apparently all finalized TDX hardware don't require the extra software-driven cache flushing around the KeyIDs but the Intel documentation was never updated to reflect that, but those Intel docs will be updated in the next revision. Intel TDX initially appeared in select Xeon Sapphire Rapids processors but has been supported by all Xeon processors since Emerald Rapids.
This leads to simpler kernel code but no word in the patch messages of any expected performance impact.
[1] https://lore.kernel.org/lkml/20261015191710.3632302-1-rick.p.edgecombe@intel.com/