GCC 17 Compiler Lands SpacemiT X100 Core Targeting
([GNU] 6 Hours Ago
SpacemiT X100)
- Reference: 0001643841
- News link: https://www.phoronix.com/news/GCC-17-SpacemiT-X100
- Source link:
The newest GCC 17 compiler code has landed support for -mcpu=spacemit-x100 and -mtune=spacemit-x100 targeting for the SpacemiT X100 RISC-V core.
The SpacemiT X100 is notable in making up the primary cores of the SpacemiT K3 SoC as the first widely-available RVA23 profile compliant RISC-V design. The K3 features eight X100 cores clocking up to 2.4GHz plus there are the eight ultra-wide parallel AI computing A100 cores.
[1]This patch now upstream in GCC from SpacemiT adds the initial X100 core support.
Also on the GCC mailing list is [2]a patch introducing the "spacemit-a100" target for -mcpu/-mtune tuning for the A100 cores too.
"Add the Spacemit-A100 processor to -mcpu/-mtune. The A100 is an in-order, dual-issue core whose microarchitecture is close to the X60, so for now it reuses the Spacemit X60 costs. On the ISA side, the A100 is closest to the X100. The main differences are that it does not implement the H (hypervisor) extension, its vector length is VLEN=1024 (zvl1024b), and it has the xsmtvdotii extension."
Considering it was just a few days from the spacemit-x100 patch going from the mailing list to working its way into GCC Git, the spacemit-a100 target will presumably also be upstreamed in short order.
In case you missed some of the SpacemiT K3 benchmarking thus far, see [3]Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX and [4]RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 .
[1] https://github.com/gcc-mirror/gcc/commit/8596c662854b8693e1e9f075b6ccee83bdcf30d7
[2] https://gcc.gnu.org/pipermail/gcc-patches/2026-June/722133.html
[3] https://www.phoronix.com/review/spacemit-k3-pico-itx
[4] https://www.phoronix.com/review/risc-v-5-year-performance
The SpacemiT X100 is notable in making up the primary cores of the SpacemiT K3 SoC as the first widely-available RVA23 profile compliant RISC-V design. The K3 features eight X100 cores clocking up to 2.4GHz plus there are the eight ultra-wide parallel AI computing A100 cores.
[1]This patch now upstream in GCC from SpacemiT adds the initial X100 core support.
Also on the GCC mailing list is [2]a patch introducing the "spacemit-a100" target for -mcpu/-mtune tuning for the A100 cores too.
"Add the Spacemit-A100 processor to -mcpu/-mtune. The A100 is an in-order, dual-issue core whose microarchitecture is close to the X60, so for now it reuses the Spacemit X60 costs. On the ISA side, the A100 is closest to the X100. The main differences are that it does not implement the H (hypervisor) extension, its vector length is VLEN=1024 (zvl1024b), and it has the xsmtvdotii extension."
Considering it was just a few days from the spacemit-x100 patch going from the mailing list to working its way into GCC Git, the spacemit-a100 target will presumably also be upstreamed in short order.
In case you missed some of the SpacemiT K3 benchmarking thus far, see [3]Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX and [4]RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3 .
[1] https://github.com/gcc-mirror/gcc/commit/8596c662854b8693e1e9f075b6ccee83bdcf30d7
[2] https://gcc.gnu.org/pipermail/gcc-patches/2026-June/722133.html
[3] https://www.phoronix.com/review/spacemit-k3-pico-itx
[4] https://www.phoronix.com/review/risc-v-5-year-performance