Linux 7.2 RISC-V Reduces Kernel Startup Overhead, Eswin SoC Support By Default
([RISC-V] 6 Hours Ago
RISC-V)
- Reference: 0001642633
- News link: https://www.phoronix.com/news/Linux-7.2-RISC-V
- Source link:
Along with the many x86/x86_64 improvements and some ARM64 architecture improvements (albeit [1]slowed down by the AI/LLM noise affecting the development pace), the RISC-V architecture changes were merged last week for the ongoing [2]Linux 7.2 kernel development.
For those using the SiFive HiFive Premier P550 or other RISC-V boards using an Eswin SoC, [3]the RISC-V default kernel configuration now enables Eswin SoC support . The RISC-V defconfig is updated to now include this Eswin SoC support with the developer motivation in wanting to ensure the default RISC-V kernel builds support the popular SiFive HiFive [4]Premier P550 board.
RISC-V meets all the requirements for HAVE_BUILDTIME_MCOUNT_SORT and by setting it, the sort table is able to sort the __mcount_loc section at link time that in turn reduces kernel start-up overhead within the ftrace initialization path.
RISC-V for this next kernel version also has a number of code clean-ups, fixing a potential memory leak in the cacheinfo code, and various fixes.
The full list of RISC-V feature changes for Linux 7.2 can be found via [5]this pull request .
[1] https://www.phoronix.com/news/ARM64-Linux-7.2-Changes
[2] https://www.phoronix.com/search/Linux+7.2
[3] https://www.phoronix.com/news/Linux-7.2-ESWIN-Default
[4] https://www.phoronix.com/search/Premier+P550
[5] https://lore.kernel.org/lkml/2ca9fd52-d4a1-5e7b-b9d9-9d759b92f8c1@kernel.org/
For those using the SiFive HiFive Premier P550 or other RISC-V boards using an Eswin SoC, [3]the RISC-V default kernel configuration now enables Eswin SoC support . The RISC-V defconfig is updated to now include this Eswin SoC support with the developer motivation in wanting to ensure the default RISC-V kernel builds support the popular SiFive HiFive [4]Premier P550 board.
RISC-V meets all the requirements for HAVE_BUILDTIME_MCOUNT_SORT and by setting it, the sort table is able to sort the __mcount_loc section at link time that in turn reduces kernel start-up overhead within the ftrace initialization path.
RISC-V for this next kernel version also has a number of code clean-ups, fixing a potential memory leak in the cacheinfo code, and various fixes.
The full list of RISC-V feature changes for Linux 7.2 can be found via [5]this pull request .
[1] https://www.phoronix.com/news/ARM64-Linux-7.2-Changes
[2] https://www.phoronix.com/search/Linux+7.2
[3] https://www.phoronix.com/news/Linux-7.2-ESWIN-Default
[4] https://www.phoronix.com/search/Premier+P550
[5] https://lore.kernel.org/lkml/2ca9fd52-d4a1-5e7b-b9d9-9d759b92f8c1@kernel.org/