GCC Git Enables Additional Tuning For AMD Zen 6
([AMD] 3 Hours Ago
AMD znver6)
- Reference: 0001638052
- News link: https://www.phoronix.com/news/GCC-More-Zen-6-Tuning-June
- Source link:
In addition to Intel [1]adjusting their Nova Lake and Diamond Rapids targets in GCC this week to deal with APX realities, AMD this week also adjusted some tuning bits for their Zen 6 " [2]znver6 " target.
These newly-enabled tunings for Zen 6 now fuse ALU with a subsequent conditional jump instruction when the ALU contains a memory operand, fusing ALU with a subsequent conditional jump instruction when the ALU contains both immediate and displacement, and lastly prefering PSHUF to reduce V16QI, V8HI, V8HI, V4SI, V4FI, V2DI modes when LSHR are costlier.
These tunings were already enabled in the GNU Compiler Collection for AMD Zen 4 and Zen 5 processors. So it's a bit surprising these tunings weren't carried over when landing Znver6 in the first place. Also unfortunate that it's coming after the GCC 16.1 stable release where the initial Znver6 support was introduced. Similarly we are still waiting on the Znver6 optimized cost tables / scheduler model to be introduced to the open-source compilers rather than just re-using the prior Zen 4/5 data.
In any event [3]this commit has the latest Znver6 tunings now in GCC 17 Git. Presumably this patch will also get back-ported for the GCC 15.2 point release in the coming months.
[1] https://www.phoronix.com/news/Intel-APX-GCC-Disabling-Bits
[2] https://www.phoronix.com/search/znver6
[3] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=ff3ae0cd90e5d6e9347c467ec8881781779171e2
These newly-enabled tunings for Zen 6 now fuse ALU with a subsequent conditional jump instruction when the ALU contains a memory operand, fusing ALU with a subsequent conditional jump instruction when the ALU contains both immediate and displacement, and lastly prefering PSHUF to reduce V16QI, V8HI, V8HI, V4SI, V4FI, V2DI modes when LSHR are costlier.
These tunings were already enabled in the GNU Compiler Collection for AMD Zen 4 and Zen 5 processors. So it's a bit surprising these tunings weren't carried over when landing Znver6 in the first place. Also unfortunate that it's coming after the GCC 16.1 stable release where the initial Znver6 support was introduced. Similarly we are still waiting on the Znver6 optimized cost tables / scheduler model to be introduced to the open-source compilers rather than just re-using the prior Zen 4/5 data.
In any event [3]this commit has the latest Znver6 tunings now in GCC 17 Git. Presumably this patch will also get back-ported for the GCC 15.2 point release in the coming months.
[1] https://www.phoronix.com/news/Intel-APX-GCC-Disabling-Bits
[2] https://www.phoronix.com/search/znver6
[3] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=ff3ae0cd90e5d6e9347c467ec8881781779171e2