Some Elements Of Intel APX Not Proving Beneficial On Nova Lake / Diamond Rapids
([Intel] 6 Hours Ago
Advanced Performance Extensions)
- Reference: 0001637179
- News link: https://www.phoronix.com/news/Intel-APX-GCC-Disabling-Bits
- Source link:
Some compiler tuning merged today to the GNU Compiler Collection (GCC) is disabling some features of [1]Advanced Performance Extensions (APX) for upcoming Intel Nova Lake and Diamond Rapids processors as they are not proving worthwhile for performance.
Intel compiler engineer Hongyu Wang upstreamed two patches so far today for additional tuning to the existing Nova Lake and Diamond Rapids targets in this prominent open-source compiler. Interestingly the tuning is to avoid some attributes of the new APX functionality for portions not panning out performance wise. APX is a big upgrade to the x86 instruction set debuting with these next-gen processors. Some areas will be a definite win like doubling the number of general purpose registers and some of the new instructions, but given today's compiler tuning it sounds like the initial roll-out isn't an absolute slam dunk.
[2]This patch ends up disabling memory-form NDD of Intel APX for Nova Lake:
"Benchmark shows memory form of NDD instructions is not beneficial on NovaLake. Add X86_TUNE_ENABLE_NDD_MEM tuning (default off) to deprioritize NDD alternatives with memory source operands via the preferred_for_speed attribute. For pure NDD patterns that have a single alternative with rm constraint, split into r,m alternatives and apply preferred_for_speed on the memory alternative. For legacy patterns with NDD alternatives, also split the NDD rm constraint into separate r and m alternatives so the deprioritization targets only the memory form."
New Data Destination (NDD) is a new feature of Intel APX for upgrading some two-operand integer instructions to three-operand. But as noted, the memory-form of NDD instructions is "not beneficial on Nova Lake" and thus being disabled by default.
The other Intel tuning patch merged today to GCC Git is disabling SETcc.ZU generation on Nova Lake and Diamond Rapids. SETcc.ZU encoding is an instruction enhanced by Intel APX compared to the legacy SETcc instruction. SETZUcc is intended to bem ore efficient than executing SETcc followed by a MOVZX. But it turns out from [3]this patch that SETcc.ZU isn't providing benefit on Nova Lake and Diamond Rapids:
"Microbenchmark performance on NovaLake/DiamondRapids shows no benefit from SETcc.ZU encoding on these cores. Add X86_TUNE_DISABLE_SETZUCC to suppress setzucc generation for DMR/NVL while keeping it enabled for other APX-capable targets."
Those are the Intel tuning patches merged so far today for the GCC compiler, it will be interesting to see if any more tuning work comes out today or in the days ahead for either GCC and LLVM/Clang in preparation for Nova Lake.
[1] https://www.phoronix.com/search/Advanced+Performance+Extensions
[2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a27731f6b52d94f4b1461709409057ab2a8a31ae
[3] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8ff497c904bb363e52d57c108eba2675d1bcde14
Intel compiler engineer Hongyu Wang upstreamed two patches so far today for additional tuning to the existing Nova Lake and Diamond Rapids targets in this prominent open-source compiler. Interestingly the tuning is to avoid some attributes of the new APX functionality for portions not panning out performance wise. APX is a big upgrade to the x86 instruction set debuting with these next-gen processors. Some areas will be a definite win like doubling the number of general purpose registers and some of the new instructions, but given today's compiler tuning it sounds like the initial roll-out isn't an absolute slam dunk.
[2]This patch ends up disabling memory-form NDD of Intel APX for Nova Lake:
"Benchmark shows memory form of NDD instructions is not beneficial on NovaLake. Add X86_TUNE_ENABLE_NDD_MEM tuning (default off) to deprioritize NDD alternatives with memory source operands via the preferred_for_speed attribute. For pure NDD patterns that have a single alternative with rm constraint, split into r,m alternatives and apply preferred_for_speed on the memory alternative. For legacy patterns with NDD alternatives, also split the NDD rm constraint into separate r and m alternatives so the deprioritization targets only the memory form."
New Data Destination (NDD) is a new feature of Intel APX for upgrading some two-operand integer instructions to three-operand. But as noted, the memory-form of NDD instructions is "not beneficial on Nova Lake" and thus being disabled by default.
The other Intel tuning patch merged today to GCC Git is disabling SETcc.ZU generation on Nova Lake and Diamond Rapids. SETcc.ZU encoding is an instruction enhanced by Intel APX compared to the legacy SETcc instruction. SETZUcc is intended to bem ore efficient than executing SETcc followed by a MOVZX. But it turns out from [3]this patch that SETcc.ZU isn't providing benefit on Nova Lake and Diamond Rapids:
"Microbenchmark performance on NovaLake/DiamondRapids shows no benefit from SETcc.ZU encoding on these cores. Add X86_TUNE_DISABLE_SETZUCC to suppress setzucc generation for DMR/NVL while keeping it enabled for other APX-capable targets."
Those are the Intel tuning patches merged so far today for the GCC compiler, it will be interesting to see if any more tuning work comes out today or in the days ahead for either GCC and LLVM/Clang in preparation for Nova Lake.
[1] https://www.phoronix.com/search/Advanced+Performance+Extensions
[2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a27731f6b52d94f4b1461709409057ab2a8a31ae
[3] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8ff497c904bb363e52d57c108eba2675d1bcde14