Hygon C86-4G CPU Support Added To The GCC 17 Compiler
([GNU] 3 Hours Ago
HYGON C86-4G)
- Reference: 0001630716
- News link: https://www.phoronix.com/news/Hygon-C86-4G-CPU-GCC-17
- Source link:
Merged today to the GCC Git compiler codebase, which will be for GCC 17 rather than the imminent GCC 16.1 stable release, is adding support for the Chinese-manufactured Hygon C86-4G-M4 / C86-4G-M6 / C86-4G-M7 series x86_64 processors.
Hygon is the Chinese company that began producing x86-compatible processors thanks to the AMD-Chinese Joint Venture during the Zen 1 days. Hygon has continued working on new processors and last year merged with server maker Sugon.
Hygon's C86-4G processor has been known since at least last year for offering 16 cores / 32 threads and delivering performance comparable to Intel Raptor Lake CPUs while supporting DDR5 and PCIe Gen 5. Hygon has claimed that C86-4G employs a new "self-developed microarchitecture" though going through the GCC compiler patch indicates many similarities still with AMD Zen.
The compiler patch does also (obviously) confirm the CPU ISA capabilities of the C86-4G-M4 / C86-4G-M6 / C86-4G-M7 families. Most notable is with C86-4G-M7 having AVX-512 support while there are no instruction set differences between the M4 and M6 families.
c86-4g-m4
HYGON c86-4g-m4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3, SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA, XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO, CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
c86-4g-m6
HYGON c86-4g-m6 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3, SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA, XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO, CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
c86-4g-m7
HYGON c86-4g-m7 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3, SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA, XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO, CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD, AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES, AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ, WBNOINVD instruction set support.
The GCC compiler patch for these Hygon CPUs allows proper detection with -march=native handling as well as introducing new CPU target options of c86-4g-m4, c86-4g-m6, and c86-4g-m7 for targeting these Chinese x86 processors.
Those interested in digging into the Hygon C86-4G compiler support and instruction / cost tables to compare against AMD Zen and the like can do so via [1]this GCC commit .
[1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=2a64a63d982584618af1de1b5d5f1f1c3ec03502
Hygon is the Chinese company that began producing x86-compatible processors thanks to the AMD-Chinese Joint Venture during the Zen 1 days. Hygon has continued working on new processors and last year merged with server maker Sugon.
Hygon's C86-4G processor has been known since at least last year for offering 16 cores / 32 threads and delivering performance comparable to Intel Raptor Lake CPUs while supporting DDR5 and PCIe Gen 5. Hygon has claimed that C86-4G employs a new "self-developed microarchitecture" though going through the GCC compiler patch indicates many similarities still with AMD Zen.
The compiler patch does also (obviously) confirm the CPU ISA capabilities of the C86-4G-M4 / C86-4G-M6 / C86-4G-M7 families. Most notable is with C86-4G-M7 having AVX-512 support while there are no instruction set differences between the M4 and M6 families.
c86-4g-m4
HYGON c86-4g-m4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3, SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA, XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO, CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
c86-4g-m6
HYGON c86-4g-m6 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3, SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA, XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO, CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
c86-4g-m7
HYGON c86-4g-m7 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3, SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA, XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO, CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD, AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES, AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ, WBNOINVD instruction set support.
The GCC compiler patch for these Hygon CPUs allows proper detection with -march=native handling as well as introducing new CPU target options of c86-4g-m4, c86-4g-m6, and c86-4g-m7 for targeting these Chinese x86 processors.
Those interested in digging into the Hygon C86-4G compiler support and instruction / cost tables to compare against AMD Zen and the like can do so via [1]this GCC commit .
[1] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=2a64a63d982584618af1de1b5d5f1f1c3ec03502