LLVM/Clang 22 Feature Development Ends With Intel Nova Lake, Arm C1 & Ampere1C Support
([LLVM] 13 January 05:59 AM EST
Clang 22)
- Reference: 0001605769
- News link: https://www.phoronix.com/news/LLVM-Clang-22-Branched
- Source link:
LLVM/Clang 22 feature development ended overnight with the code now being branched and working toward a stable release likely by the end of February.
LLVM/Clang 22 was branched and thus feature development is over as now they begin working on the release candidate phase with bug fixing. This half-year update to the LLVM compiler stack brings a lot of new hardware support, various new compiler features and language support, and other enhancements.
Some of the LLVM 22 highlights include:
- Clang now supports Named Loops for C2y, among other early C2y language work.
- More SSE, AVX, and AVX-512 intrinsics can now be used in C++ constant expressions. Some intrinsics have also been converted to wrap __builtin intrinsics.
- [1]Clang support for Ampere Computing's Ampere1C CPUs . Ampere-1C processor cores are likely for Ampere Aurora.
- Dropping the AVX10 256-bit vs. 512-bit options now that Intel thankfully abandoned their AVX10 256-bit only plans.
- There is support for Intel Wildcat Lake with -march=wildcatlake and [2]Intel Nova Lake with -march=novalake with APX and AVX10.2 .
- [3]Some long overdue optimizations for AMD Zen 4 .
- Clang on ARM64 now supports the Arm C1 Nano, C1 Pro, C1 Prmeium, and C1 Ultra processors.
- LLVM assembler and disassembler support for Armv9.7-A (2025) architecture extensions.
- RISC-V support for Zvfbfa for additional BF16 vector compute support.
- [4]NVIDIA Olympus CPU scheduling model is added.
- Intel [5]upstreamed the libsycl SYCL Runtime Library .
- LLVM 22 began seeing [6]Distributed ThinLTO "DTLTO" support upstreaming .
- AMD contributed [7]BFloat16 for LLVM's SPIR-V target .
- The Ssctr and Smctr RISC-V extensions are also deemed no longer experimental nor are [8]Qualcomm's Xqci and Xqccmp vendor extensions.
- LLVM 22 has finally [9]eliminated the last support for Google Native Client (NaCl).
LLVM Clang 23 meanwhile is now under feature development in LLVM Git.
LLVM 22 release candidates will begin soon with an aim of allowing LLVM Clang 22.1 stable to hopefully be released by the end of February.
[1] https://www.phoronix.com/news/LLVM-Clang-Ampere1C
[2] https://www.phoronix.com/news/LLVM-Clang-NVL-APX-AVX-10.2
[3] https://www.phoronix.com/news/LLVM-Overdue-Znver4-Tuning
[4] https://www.phoronix.com/news/NVIDIA-Olympus-Sched-Model
[5] https://www.phoronix.com/news/LLVM-Upstream-libsycl
[6] https://www.phoronix.com/news/LLVM-DTLTO-Distributed-Thin
[7] https://www.phoronix.com/news/AMD-BF16-For-LLVM-SPIR-V
[8] https://www.phoronix.com/news/Qualcomm-Xqci-LLVM-Stable
[9] https://www.phoronix.com/news/LLVM-22-Removes-Native-Client
LLVM/Clang 22 was branched and thus feature development is over as now they begin working on the release candidate phase with bug fixing. This half-year update to the LLVM compiler stack brings a lot of new hardware support, various new compiler features and language support, and other enhancements.
Some of the LLVM 22 highlights include:
- Clang now supports Named Loops for C2y, among other early C2y language work.
- More SSE, AVX, and AVX-512 intrinsics can now be used in C++ constant expressions. Some intrinsics have also been converted to wrap __builtin intrinsics.
- [1]Clang support for Ampere Computing's Ampere1C CPUs . Ampere-1C processor cores are likely for Ampere Aurora.
- Dropping the AVX10 256-bit vs. 512-bit options now that Intel thankfully abandoned their AVX10 256-bit only plans.
- There is support for Intel Wildcat Lake with -march=wildcatlake and [2]Intel Nova Lake with -march=novalake with APX and AVX10.2 .
- [3]Some long overdue optimizations for AMD Zen 4 .
- Clang on ARM64 now supports the Arm C1 Nano, C1 Pro, C1 Prmeium, and C1 Ultra processors.
- LLVM assembler and disassembler support for Armv9.7-A (2025) architecture extensions.
- RISC-V support for Zvfbfa for additional BF16 vector compute support.
- [4]NVIDIA Olympus CPU scheduling model is added.
- Intel [5]upstreamed the libsycl SYCL Runtime Library .
- LLVM 22 began seeing [6]Distributed ThinLTO "DTLTO" support upstreaming .
- AMD contributed [7]BFloat16 for LLVM's SPIR-V target .
- The Ssctr and Smctr RISC-V extensions are also deemed no longer experimental nor are [8]Qualcomm's Xqci and Xqccmp vendor extensions.
- LLVM 22 has finally [9]eliminated the last support for Google Native Client (NaCl).
LLVM Clang 23 meanwhile is now under feature development in LLVM Git.
LLVM 22 release candidates will begin soon with an aim of allowing LLVM Clang 22.1 stable to hopefully be released by the end of February.
[1] https://www.phoronix.com/news/LLVM-Clang-Ampere1C
[2] https://www.phoronix.com/news/LLVM-Clang-NVL-APX-AVX-10.2
[3] https://www.phoronix.com/news/LLVM-Overdue-Znver4-Tuning
[4] https://www.phoronix.com/news/NVIDIA-Olympus-Sched-Model
[5] https://www.phoronix.com/news/LLVM-Upstream-libsycl
[6] https://www.phoronix.com/news/LLVM-DTLTO-Distributed-Thin
[7] https://www.phoronix.com/news/AMD-BF16-For-LLVM-SPIR-V
[8] https://www.phoronix.com/news/Qualcomm-Xqci-LLVM-Stable
[9] https://www.phoronix.com/news/LLVM-22-Removes-Native-Client