Qualcomm's Xqci RISC-V Extension Now Deemed Non-Experimental For LLVM 22
([LLVM] 2 Minutes Ago
Qualcomm Xqci)
- Reference: 0001601465
- News link: https://www.phoronix.com/news/Qualcomm-Xqci-LLVM-Stable
- Source link:
In LLVM Git yesterday for next year's LLVM 22 release the Qualcomm Xqci RISC-V vendor extension is no longer deemed experimental.
Xqci is a Qualcomm extension designed for RISC-V micro-controllers. Xqci fills in gaps of RISC_V functionality around embedded and micro-controller needs for interrupt handling, load/store differences, and various other new instructions. Qualcomm sums up Xqci [1]as :
"This extension contains a lot of new instructions, for a variety of uses from simple bit manipulation instructions to memory accesses with wider offsets, and new branches and jumps."
With LLVM 20 adding assembler support for this vendor extension and code generation in LLVM 21, for LLVM 22 it's no longer going to be considered experimental.
[2]This LLVM commit by Qualcomm engineer Sudharsan Veeravalli promotes this important micro-controller RISC-V extension to being non-experimental.
Qualcomm has been making many RISC-V investments and with their recent [3]acquisition of Ventana it will be interesting to see what new announcement come out of the company in the new year.
[1] https://www.qualcomm.com/developer/blog/2025/09/llvm-21-improvements-for-qualcomms-platforms
[2] https://github.com/llvm/llvm-project/commit/520ba7d0e5cb4b1ad0d6927d6aeb9a3dfd5d26de
[3] https://www.phoronix.com/news/Qualcomm-Acquires-Ventana
Xqci is a Qualcomm extension designed for RISC-V micro-controllers. Xqci fills in gaps of RISC_V functionality around embedded and micro-controller needs for interrupt handling, load/store differences, and various other new instructions. Qualcomm sums up Xqci [1]as :
"This extension contains a lot of new instructions, for a variety of uses from simple bit manipulation instructions to memory accesses with wider offsets, and new branches and jumps."
With LLVM 20 adding assembler support for this vendor extension and code generation in LLVM 21, for LLVM 22 it's no longer going to be considered experimental.
[2]This LLVM commit by Qualcomm engineer Sudharsan Veeravalli promotes this important micro-controller RISC-V extension to being non-experimental.
Qualcomm has been making many RISC-V investments and with their recent [3]acquisition of Ventana it will be interesting to see what new announcement come out of the company in the new year.
[1] https://www.qualcomm.com/developer/blog/2025/09/llvm-21-improvements-for-qualcomms-platforms
[2] https://github.com/llvm/llvm-project/commit/520ba7d0e5cb4b1ad0d6927d6aeb9a3dfd5d26de
[3] https://www.phoronix.com/news/Qualcomm-Acquires-Ventana