Linux Preps For Kunpeng ARM Server SoC With High Bandwidth Memory
([Hardware] 117 Minutes Ago
Huawei Kunpeng SoC With HBM)
- Reference: 0001510719
- News link: https://www.phoronix.com/news/Huawei-Kunpeng-HBM-Linux
- Source link:
New Linux patches from Huawei engineers are preparing new driver support for controlling High Bandwidth Memory (HBM) with the ARM-based Kunpeng high performance SoC.
Huawei's Kunpeng SoC so far has been in the form of the Kunpeng 920 as an aging 7nm CPU with up to 64 cores based on Armv8.2. The Kunpeng 920 supports eight channels of DDR4 memory and has up to a 180 Watt TDP. The specs aren't interesting as we approach 2025 but it would appear there is a new Kunpeng SoC coming that will feature integrated High Bandwidth Memory (HBM).
Unless I missed something, this Kunpeng SoC with HBM memory hasn't been formally announced yet and I haven't been able to find any other references short of pointing to prior kernel patches working on this HBM integration. The patches out today are adding power control support for the HBM memory on the Kunpeng SoC and the ability to online/offline this cache.
The [1]patch series from Huawei explains of this HBM support on the unspecified Kunpeng SoC:
"Add power control support for High Bandwidth Memory (HBM) for Kunpeng SoC platform. HBM devices on Kunpeng SoC can provide higher bandwidth at the cost of higher power consumption. Providing power control methods can help reducing the power when the workload does not need use HBM.
...
Add a driver for High Bandwidth Memory (HBM) devices, which will provide user space interfaces to power on/off the HBM devices. In Kunpeng servers, we need to control the power of HBM devices which can be power consuming and will only be used in some specialized scenarios, such as HPC. HBM memory devices in a socket are in the same power domain, and should be power off/on together.
...
Add a driver for High Bandwidth Memory (HBM) cache, which provides user space interfaces to power on/off the HBM cache. Use HBM as a cache can take advantage of the high bandwidth of HBM in normal memory access, and OS does not need to aware of the existence of HBM cache. For workloads which does not require a high memory access bandwidth, power off the HBM cache device can help save energy."
It will be interesting to see what comes of Huawei Kunpeng SoCs with HBM memory and ultimately how well they perform against other AArch64 server processors as well as the Intel Xeon and AMD EPYC competition.
[1] https://lore.kernel.org/lkml/20241206112812.32618-1-zhangzekun11@huawei.com/
Huawei's Kunpeng SoC so far has been in the form of the Kunpeng 920 as an aging 7nm CPU with up to 64 cores based on Armv8.2. The Kunpeng 920 supports eight channels of DDR4 memory and has up to a 180 Watt TDP. The specs aren't interesting as we approach 2025 but it would appear there is a new Kunpeng SoC coming that will feature integrated High Bandwidth Memory (HBM).
Unless I missed something, this Kunpeng SoC with HBM memory hasn't been formally announced yet and I haven't been able to find any other references short of pointing to prior kernel patches working on this HBM integration. The patches out today are adding power control support for the HBM memory on the Kunpeng SoC and the ability to online/offline this cache.
The [1]patch series from Huawei explains of this HBM support on the unspecified Kunpeng SoC:
"Add power control support for High Bandwidth Memory (HBM) for Kunpeng SoC platform. HBM devices on Kunpeng SoC can provide higher bandwidth at the cost of higher power consumption. Providing power control methods can help reducing the power when the workload does not need use HBM.
...
Add a driver for High Bandwidth Memory (HBM) devices, which will provide user space interfaces to power on/off the HBM devices. In Kunpeng servers, we need to control the power of HBM devices which can be power consuming and will only be used in some specialized scenarios, such as HPC. HBM memory devices in a socket are in the same power domain, and should be power off/on together.
...
Add a driver for High Bandwidth Memory (HBM) cache, which provides user space interfaces to power on/off the HBM cache. Use HBM as a cache can take advantage of the high bandwidth of HBM in normal memory access, and OS does not need to aware of the existence of HBM cache. For workloads which does not require a high memory access bandwidth, power off the HBM cache device can help save energy."
It will be interesting to see what comes of Huawei Kunpeng SoCs with HBM memory and ultimately how well they perform against other AArch64 server processors as well as the Intel Xeon and AMD EPYC competition.
[1] https://lore.kernel.org/lkml/20241206112812.32618-1-zhangzekun11@huawei.com/
phoronix